It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen withexisting platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform’s native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.
Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalkcauses inadvertent driving of quantum gates, which will adversely affect quantum-gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than -27 dB (average -37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13 % direct-current flux crosstalk (average 0.05 %). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implication of our results for the design of a low-crosstalk, on-chip signal delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors.
We demonstrate aluminum-on-silicon planar transmon qubits with time-averaged T1 energy relaxation times of up to 270μs, corresponding to Q = 5 million, and a highest observed valueof 501μs. We use materials analysis techniques and numerical simulations to investigate the dominant sources of energy loss, and devise and demonstrate a strategy towards mitigating them. The mitigation of loss is achieved by reducing the presence of oxide, a known host of defects, near the substrate-metal interface, by growing aluminum films thicker than 300 nm. A loss analysis of coplanar-waveguide resonators shows that the improvement is owing to a reduction of dielectric loss due to two-level system defects. We perform time-of-flight secondary ion mass spectrometry and observe a reduced presence of oxygen at the substrate-metal interface for the thicker films. The correlation between the enhanced performance and the film thickness is due to the tendency of aluminum to grow in columnar structures of parallel grain boundaries, where the size of the grain depends on the film thickness: transmission electron microscopy imaging shows that the thicker film has larger grains and consequently fewer grain boundaries containing oxide near this interface. These conclusions are supported by numerical simulations of the different loss contributions in the device.
While all quantum algorithms can be expressed in terms of single-qubit and two-qubit gates, more expressive gate sets can help reduce the algorithmic depth. This is important in thepresence of gate errors, especially those due to decoherence. Using superconducting qubits, we have implemented a three-qubit gate by simultaneously applying two-qubit operations, thereby realizing a three-body interaction. This method straightforwardly extends to other quantum hardware architectures, requires only a „firmware“ upgrade to implement, and is faster than its constituent two-qubit gates. The three-qubit gate represents an entire family of operations, creating flexibility in quantum-circuit compilation. We demonstrate a gate fidelity of 97.90%, which is near the coherence limit of our device. We then generate two classes of entangled states, the GHZ and W states, by applying the new gate only once; in comparison, decompositions into the standard gate set would have a two-qubit gate depth of two and three, respectively. Finally, we combine characterization methods and analyze the experimental and statistical errors on the fidelity of the gates and of the target states.
We describe a digital microwave platform called Presto, designed for measurement and control of multiple quantum bits (qubits) and based on the third-generation radio-frequency systemon a chip. Presto uses direct digital synthesis to create signals up to 9 GHz on 16 synchronous output ports, while synchronously analyzing response on 16 input ports. Presto has 16 DC-bias outputs, 4 inputs and 4 outputs for digital triggers or markers, and two continuous-wave outputs for synthesizing frequencies up to 15 GHz. Scaling to a large number of qubits is enabled through deterministic synchronization of multiple Presto units. A Python application programming interface configures a firmware for synthesis and analysis of pulses, coordinated by an event sequencer. The analysis integrates template matching (matched filtering) and low-latency (184 – 254 ns) feedback to enable a wide range of multi-qubit experiments. We demonstrate Presto’s capabilities with experiments on a sample consisting of two superconducting qubits connected via a flux-tunable coupler. We show single-shot readout and active reset of a single qubit; randomized benchmarking of single-qubit gates showing 99.972% fidelity, limited by the coherence time of the qubit; and calibration of a two-qubit iSWAP gate.
We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips – one quantum chip and one control chip –that are bump-bonded together. We demonstrate time-averaged coherence times exceeding 90μs, single-qubit gate fidelities exceeding 99.9%, and two-qubit gate fidelities above 98.6%. We also present device design methods and discuss the sensitivity of device parameters to variation in interchip spacing. Notably, the additional flip-chip fabrication steps do not degrade the qubit performance compared to our baseline state-of-the-art in single-chip, planar circuits. This integration technique can be extended to the realisation of quantum processors accommodating hundreds of qubits in one module as it offers adequate input/output wiring access to all qubits and couplers.
Present-day, noisy, small or intermediate-scale quantum processors—although far from fault-tolerant—support the execution of heuristic quantum algorithms, which might enablea quantum advantage, for example, when applied to combinatorial optimization problems. On small-scale quantum processors, validations of such algorithms serve as important technology demonstrators. We implement the quantum approximate optimization algorithm (QAOA) on our hardware platform, consisting of two transmon qubits and one parametrically modulated coupler. We solve small instances of the NP-complete exact-cover problem, with 96.6\% success probability, by iterating the algorithm up to level two.