In superconducting quantum processors, the predictability of device parameters is of increasing importance as many labs scale up their systems to larger sizes in a 3D-integrated architecture.In particular, the properties of superconducting resonators must be controlled well to ensure high-fidelity multiplexed readout of qubits. Here we present a method, based on conformal mapping techniques, to predict a resonator’s parameters directly from its 2D cross-section, without computationally heavy simulation. We demonstrate the method’s validity by comparing the calculated resonator frequency and coupling quality factor with those obtained through 3D finite-element-method simulation and by measurement of 15 resonators in a flip-chip-integrated architecture. We achieve a discrepancy of less than 2% between designed and measured frequencies, for 6-GHz resonators. We also propose a design method that reduces the sensitivity of the resonant frequency to variations in the inter-chip spacing.
We report the implementation of a near-quantum-limited, traveling-wave parametric amplifier that uses three-wave mixing (3WM). To favor amplification by 3WM, we use the superconductingnonlinear asymmetric inductive element (SNAIL) loops, biased with a dc magnetic flux. In addition, we equip the device with dispersion engineering features to create a stop-band at the second harmonic of the pump and suppress the propagation of the higher harmonics that otherwise degrade the amplification. With a chain of 440 SNAILs, the amplifier provides up to 20 dB gain and a 3-dB bandwidth of 1 GHz. The added noise by the amplifier is found to be less than one photon.
We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips – one quantum chip and one control chip –that are bump-bonded together. We demonstrate time-averaged coherence times exceeding 90μs, single-qubit gate fidelities exceeding 99.9%, and two-qubit gate fidelities above 98.6%. We also present device design methods and discuss the sensitivity of device parameters to variation in interchip spacing. Notably, the additional flip-chip fabrication steps do not degrade the qubit performance compared to our baseline state-of-the-art in single-chip, planar circuits. This integration technique can be extended to the realisation of quantum processors accommodating hundreds of qubits in one module as it offers adequate input/output wiring access to all qubits and couplers.
Present-day, noisy, small or intermediate-scale quantum processors—although far from fault-tolerant—support the execution of heuristic quantum algorithms, which might enablea quantum advantage, for example, when applied to combinatorial optimization problems. On small-scale quantum processors, validations of such algorithms serve as important technology demonstrators. We implement the quantum approximate optimization algorithm (QAOA) on our hardware platform, consisting of two transmon qubits and one parametrically modulated coupler. We solve small instances of the NP-complete exact-cover problem, with 96.6\% success probability, by iterating the algorithm up to level two.