Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalkcauses inadvertent driving of quantum gates, which will adversely affect quantum-gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than -27 dB (average -37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13 % direct-current flux crosstalk (average 0.05 %). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implication of our results for the design of a low-crosstalk, on-chip signal delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors.

The reproducibility of qubit parameters is a challenge for scaling up superconducting quantum processors. Signal crosstalk imposes constraints on the frequency separation between neighboringqubits. The frequency uncertainty of transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction area, tunnel barrier thickness, and the qubit capacitor. We decrease the sensitivity to these variations by fabricating larger Josephson junctions and reduce the wafer-level standard deviation in resistance down to 2%. We characterize 32 identical transmon qubits and demonstrate the reproducibility of the qubit frequencies with a 40 MHz standard deviation (i.e. 1%) with qubit quality factors exceeding 2 million. We perform two-level-system (TLS) spectroscopy and observe no significant increase in the number of TLSs causing qubit relaxation. We further show by simulation that for our parametric-gate architecture, and accounting only for errors caused by the uncertainty of the qubit frequency, we can scale up to 100 qubits with an average of only 3 collisions between quantum-gate transition frequencies, assuming 2% crosstalk and 99.9% target gate fidelity.

While all quantum algorithms can be expressed in terms of single-qubit and two-qubit gates, more expressive gate sets can help reduce the algorithmic depth. This is important in thepresence of gate errors, especially those due to decoherence. Using superconducting qubits, we have implemented a three-qubit gate by simultaneously applying two-qubit operations, thereby realizing a three-body interaction. This method straightforwardly extends to other quantum hardware architectures, requires only a „firmware“ upgrade to implement, and is faster than its constituent two-qubit gates. The three-qubit gate represents an entire family of operations, creating flexibility in quantum-circuit compilation. We demonstrate a gate fidelity of 97.90%, which is near the coherence limit of our device. We then generate two classes of entangled states, the GHZ and W states, by applying the new gate only once; in comparison, decompositions into the standard gate set would have a two-qubit gate depth of two and three, respectively. Finally, we combine characterization methods and analyze the experimental and statistical errors on the fidelity of the gates and of the target states.

We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips – one quantum chip and one control chip –that are bump-bonded together. We demonstrate time-averaged coherence times exceeding 90μs, single-qubit gate fidelities exceeding 99.9%, and two-qubit gate fidelities above 98.6%. We also present device design methods and discuss the sensitivity of device parameters to variation in interchip spacing. Notably, the additional flip-chip fabrication steps do not degrade the qubit performance compared to our baseline state-of-the-art in single-chip, planar circuits. This integration technique can be extended to the realisation of quantum processors accommodating hundreds of qubits in one module as it offers adequate input/output wiring access to all qubits and couplers.