It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen withexisting platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform’s native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.
Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalkcauses inadvertent driving of quantum gates, which will adversely affect quantum-gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than -27 dB (average -37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13 % direct-current flux crosstalk (average 0.05 %). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implication of our results for the design of a low-crosstalk, on-chip signal delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors.
We systematically investigate the influence of the fabrication process on dielectric loss in aluminum-on-silicon superconducting coplanar waveguide resonators with internal qualityfactors (Qi) of about one million at the single-photon level. These devices are essential components in superconducting quantum processors; they also serve as proxies for understanding the energy loss of superconducting qubits. By systematically varying several fabrication steps, we identify the relative importance of reducing loss at the substrate-metal and the substrate-air interfaces. We find that it is essential to clean the silicon substrate in hydrogen fluoride (HF) prior to aluminum deposition. A post-fabrication removal of the oxides on the surface of the silicon substrate and the aluminum film by immersion in HF further improves the Qi. We observe a small, but noticeable, adverse effect on the loss by omitting either standard cleaning (SC1), pre-deposition heating of the substrate to 300°C, or in-situ post-deposition oxidation of the film’s top surface. We find no improvement due to excessive pumping meant to reach a background pressure below 6×10−8 mbar. We correlate the measured loss with microscopic properties of the substrate-metal interface through characterization with X-ray photoelectron spectroscopy (XPS), time-of-flight secondary ion mass spectroscopy (ToF-SIMS), transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (EDS), and atomic force microscopy (AFM).
We demonstrate aluminum-on-silicon planar transmon qubits with time-averaged T1 energy relaxation times of up to 270μs, corresponding to Q = 5 million, and a highest observed valueof 501μs. We use materials analysis techniques and numerical simulations to investigate the dominant sources of energy loss, and devise and demonstrate a strategy towards mitigating them. The mitigation of loss is achieved by reducing the presence of oxide, a known host of defects, near the substrate-metal interface, by growing aluminum films thicker than 300 nm. A loss analysis of coplanar-waveguide resonators shows that the improvement is owing to a reduction of dielectric loss due to two-level system defects. We perform time-of-flight secondary ion mass spectrometry and observe a reduced presence of oxygen at the substrate-metal interface for the thicker films. The correlation between the enhanced performance and the film thickness is due to the tendency of aluminum to grow in columnar structures of parallel grain boundaries, where the size of the grain depends on the film thickness: transmission electron microscopy imaging shows that the thicker film has larger grains and consequently fewer grain boundaries containing oxide near this interface. These conclusions are supported by numerical simulations of the different loss contributions in the device.
In superconducting quantum processors, the predictability of device parameters is of increasing importance as many labs scale up their systems to larger sizes in a 3D-integrated architecture.In particular, the properties of superconducting resonators must be controlled well to ensure high-fidelity multiplexed readout of qubits. Here we present a method, based on conformal mapping techniques, to predict a resonator’s parameters directly from its 2D cross-section, without computationally heavy simulation. We demonstrate the method’s validity by comparing the calculated resonator frequency and coupling quality factor with those obtained through 3D finite-element-method simulation and by measurement of 15 resonators in a flip-chip-integrated architecture. We achieve a discrepancy of less than 2% between designed and measured frequencies, for 6-GHz resonators. We also propose a design method that reduces the sensitivity of the resonant frequency to variations in the inter-chip spacing.
We report the implementation of a near-quantum-limited, traveling-wave parametric amplifier that uses three-wave mixing (3WM). To favor amplification by 3WM, we use the superconductingnonlinear asymmetric inductive element (SNAIL) loops, biased with a dc magnetic flux. In addition, we equip the device with dispersion engineering features to create a stop-band at the second harmonic of the pump and suppress the propagation of the higher harmonics that otherwise degrade the amplification. With a chain of 440 SNAILs, the amplifier provides up to 20 dB gain and a 3-dB bandwidth of 1 GHz. The added noise by the amplifier is found to be less than one photon.
High-fidelity and rapid readout of a qubit state is key to quantum computing and communication, and it is a prerequisite for quantum error correction. We present a readout scheme forsuperconducting qubits that combines two microwave techniques: applying a shelving technique to the qubit that effectively increases the energy-relaxation time, and a two-tone excitation of the readout resonator to distinguish among qubit populations in higher energy levels. Using a machine-learning algorithm to post-process the two-tone measurement results further improves the qubit-state assignment fidelity. We perform single-shot frequency-multiplexed qubit readout, with a 140ns readout time, and demonstrate 99.5% assignment fidelity for two-state readout and 96.9% for three-state readout – without using a quantum-limited amplifier.
We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips – one quantum chip and one control chip –that are bump-bonded together. We demonstrate time-averaged coherence times exceeding 90μs, single-qubit gate fidelities exceeding 99.9%, and two-qubit gate fidelities above 98.6%. We also present device design methods and discuss the sensitivity of device parameters to variation in interchip spacing. Notably, the additional flip-chip fabrication steps do not degrade the qubit performance compared to our baseline state-of-the-art in single-chip, planar circuits. This integration technique can be extended to the realisation of quantum processors accommodating hundreds of qubits in one module as it offers adequate input/output wiring access to all qubits and couplers.