It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen withexisting platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform’s native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.
Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalkcauses inadvertent driving of quantum gates, which will adversely affect quantum-gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than -27 dB (average -37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13 % direct-current flux crosstalk (average 0.05 %). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implication of our results for the design of a low-crosstalk, on-chip signal delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors.
High-fidelity and rapid readout of a qubit state is key to quantum computing and communication, and it is a prerequisite for quantum error correction. We present a readout scheme forsuperconducting qubits that combines two microwave techniques: applying a shelving technique to the qubit that effectively increases the energy-relaxation time, and a two-tone excitation of the readout resonator to distinguish among qubit populations in higher energy levels. Using a machine-learning algorithm to post-process the two-tone measurement results further improves the qubit-state assignment fidelity. We perform single-shot frequency-multiplexed qubit readout, with a 140ns readout time, and demonstrate 99.5% assignment fidelity for two-state readout and 96.9% for three-state readout – without using a quantum-limited amplifier.
We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips – one quantum chip and one control chip –that are bump-bonded together. We demonstrate time-averaged coherence times exceeding 90μs, single-qubit gate fidelities exceeding 99.9%, and two-qubit gate fidelities above 98.6%. We also present device design methods and discuss the sensitivity of device parameters to variation in interchip spacing. Notably, the additional flip-chip fabrication steps do not degrade the qubit performance compared to our baseline state-of-the-art in single-chip, planar circuits. This integration technique can be extended to the realisation of quantum processors accommodating hundreds of qubits in one module as it offers adequate input/output wiring access to all qubits and couplers.