Error budget of parametric resonance entangling gate with a tunable coupler

  1. Eyob A. Sete,
  2. Vinay Tripathi,
  3. Joseph A. Valery,
  4. Daniel Lidar,
  5. and Josh Y. Mutus
We analyze the experimental error budget of parametric resonance gates in a tunable coupler architecture. We identify and characterize various sources of errors, including incoherent,
leakage, amplitude, and phase errors. By varying the two-qubit gate time, we explore the dynamics of these errors and their impact on the gate fidelity. To accurately capture the impact of incoherent errors on gate fidelity, we measure the coherence times of qubits under gate operating conditions. Our findings reveal that the incoherent errors, mainly arising from qubit relaxation and dephasing due to white noise, limit the fidelity of the two-qubit gates. Moreover, we demonstrate that leakage to noncomputational states is the second largest contributor to the two-qubit gates infidelity, as characterized using leakage-randomized benchmarking. The error budgeting methodology we developed here can be effectively applied to other types of gate implementations.

Alternating Bias Assisted Annealing of Amorphous Oxide Tunnel Junctions

  1. David P. Pappas,
  2. Mark Field,
  3. Cameron Kopas,
  4. Joel A. Howard,
  5. Xiqiao Wang,
  6. Ella Lachman,
  7. Lin Zhou,
  8. Jinsu Oh,
  9. Kameshwar Yadavalli,
  10. Eyob A. Sete,
  11. Andrew Bestwick,
  12. Matthew J. Kramer,
  13. and Joshua Y. Mutus
We demonstrate a transformational technique for controllably tuning the electrical properties of fabricated thermally oxidized amorphous aluminum-oxide tunnel junctions. Using conventional
test equipment to apply an alternating bias to a heated tunnel barrier, giant increases in the room temperature resistance, greater than 70%, can be achieved. The rate of resistance change is shown to be strongly temperature-dependent, and is independent of junction size in the sub-micron regime. In order to measure their tunneling properties at mK temperatures, we characterized transmon qubit junctions treated with this alternating-bias assisted annealing (ABAA) technique. The measured frequencies follow the Ambegaokar-Baratoff relation between the shifted resistance and critical current. Further, these studies show a reduction of junction-contributed loss on the order of ≈2×10−6, along with a significant reduction in resonant- and off-resonant-two level system defects when compared to untreated samples. Imaging with high-resolution TEM shows that the barrier is still predominantly amorphous with a more uniform distribution of aluminum coordination across the barrier relative to untreated junctions. This new approach is expected to be widely applicable to a broad range of devices that rely on amorphous aluminum oxide, as well as the many other metal-insulator-metal structures used in modern electronics.

Modular Superconducting Qubit Architecture with a Multi-chip Tunable Coupler

  1. Mark Field,
  2. Angela Q. Chen,
  3. Ben Scharmann,
  4. Eyob A. Sete,
  5. Feyza Oruc,
  6. Kim Vu,
  7. Valentin Kosenko,
  8. Joshua Y. Mutus,
  9. Stefano Poletto,
  10. and Andrew Bestwick
We use a floating tunable coupler to mediate interactions between qubits on separate chips to build a modular architecture. We demonstrate three different designs of multi-chip tunable
couplers using vacuum gap capacitors or superconducting indium bump bonds to connect the coupler to a microwave line on a common substrate and then connect to the qubit on the next chip. We show that the zero-coupling condition between qubits on separate chips can be achieved in each design and that the relaxation rates for the coupler and qubits are not noticeably affected by the extra circuit elements. Finally, we demonstrate two-qubit gate operations with fidelity at the same level as qubits with a tunable coupler on a single chip. Using one or more indium bonds does not degrade qubit coherence or impact the performance of two-qubit gates.

Hardware optimized parity check gates for superconducting surface codes

  1. Matthew J. Reagor,
  2. Thomas C. Bohdanowicz. David Rodriguez Perez,
  3. Eyob A. Sete,
  4. and William J. Zeng
Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware
are largely set by this task. Tailoring next-generation processors for joint measurements, therefore, could result in improvements to speed, accuracy, or cost — accelerating the development large-scale quantum computers. Here, we motivate such explorations by analyzing an unconventional surface code based on multi-body interactions between superconducting transmon qubits. Our central consideration, Hardware Optimized Parity (HOP) gates, achieves stabilizer-type measurements through simultaneous multi-qubit conditional phase accumulation. Despite the multi-body effects that underpin this approach, our estimates of logical faults suggest that this design can be at least as robust to realistic noise as conventional designs. We show a higher threshold of 1.25×10−3 compared to the standard code’s 0.79×10−3. However, in the HOP code the logical error rate decreases more slowly with decreasing physical error rate. Our results point to a fruitful path forward towards extending gate-model platforms for error correction at the dawn of its empirical development.

Full control of superconducting qubits with combined on-chip microwave and flux lines

  1. Riccardo Manenti,
  2. Eyob A. Sete,
  3. Angela Q. Chen,
  4. Shobhan Kulshreshtha,
  5. Jen-Hao Yeh,
  6. Feyza Oruc,
  7. Andrew Bestwick,
  8. Mark Field,
  9. Keith Jackson,
  10. and Stefano Poletto
As the field of quantum computing progresses to larger-scale devices, multiplexing will be crucial to scale quantum processors. While multiplexed readout is common practice for superconducting
devices, relatively little work has been reported about the combination of flux and microwave control lines. Here, we present a method to integrate a microwave line and a flux line into a single „XYZ line“. This combined control line allows us to perform fast single-qubit gates as well as to deliver flux signals to the qubits. The measured relaxation times of the qubits are comparable to state-of-art devices employing separate control lines. We benchmark the fidelity of single-qubit gates with randomized benchmarking, achieving a fidelity above 99.5%, and we demonstrate that XYZ lines can in principle be used to run parametric entangling gates.

Floating tunable coupler for scalable quantum computing architectures

  1. Eyob A. Sete,
  2. Angela Q. Chen,
  3. Riccardo Manenti,
  4. Shobhan Kulshreshtha,
  5. and Stefano Poletto
We propose a floating tunable coupler that does not rely on direct qubit-qubit coupling capacitances to achieve the zero-coupling condition. We show that the polarity of the qubit-coupler
couplings can be engineered to offset the otherwise constant qubit-qubit coupling and attain the zero-coupling condition when the coupler frequency is above or below the qubit frequencies. We experimentally demonstrate these two operating regimes of the tunable coupler by implementing symmetric and asymmetric configurations of the coupler’s superconducting pads with respect to the qubits. Such a floating tunable coupler provides flexibility in designing large-scale quantum processors while reducing the always-on residual couplings.

Entanglement Across Separate Silicon Dies in a Modular Superconducting Qubit Device

  1. Alysson Gold,
  2. JP Paquette,
  3. Anna Stockklauser,
  4. Matthew J. Reagor,
  5. M. Sohaib Alam,
  6. Andrew Bestwick,
  7. Nicolas Didier,
  8. Ani Nersisyan,
  9. Feyza Oruc,
  10. Armin Razavi,
  11. Ben Scharmann,
  12. Eyob A. Sete,
  13. Biswajit Sur,
  14. Davide Venturelli,
  15. Cody James Winkleblack,
  16. Filip Wudarski,
  17. Mike Harburn,
  18. and Chad Rigetti
Assembling future large-scale quantum computers out of smaller, specialized modules promises to simplify a number of formidable science and engineering challenges. One of the primary
challenges in developing a modular architecture is in engineering high fidelity, low-latency quantum interconnects between modules. Here we demonstrate a modular solid state architecture with deterministic inter-module coupling between four physically separate, interchangeable superconducting qubit integrated circuits, achieving two-qubit gate fidelities as high as 99.1±0.5\% and 98.3±0.3\% for iSWAP and CZ entangling gates, respectively. The quality of the inter-module entanglement is further confirmed by a demonstration of Bell-inequality violation for disjoint pairs of entangled qubits across the four separate silicon dies. Having proven out the fundamental building blocks, this work provides the technological foundations for a modular quantum processor: technology which will accelerate near-term experimental efforts and open up new paths to the fault-tolerant era for solid state qubit architectures.

Assessing the Influence of Broadband Instrumentation Noise on Parametrically Modulated Superconducting Qubits

  1. E. Schuyler Fried,
  2. Prasahnt Sivarajah,
  3. Nicolas Didier,
  4. Eyob A. Sete,
  5. Marcus P. da Silva,
  6. Blake R. Johnson,
  7. and Colm A. Ryan
With superconducting transmon qubits — a promising platform for quantum information processing — two-qubit gates can be performed using AC signals to modulate a tunable
transmon’s frequency via magnetic flux through its SQUID loop. However, frequency tunablity introduces an additional dephasing mechanism from magnetic fluctuations. In this work, we experimentally study the contribution of instrumentation noise to flux instability and the resulting error rate of parametrically activated two-qubit gates. Specifically, we measure the qubit coherence time under flux modulation while injecting broadband noise through the flux control channel. We model the noise’s effect using a dephasing rate model that matches well to the measured rates, and use it to prescribe a noise floor required to achieve a desired two-qubit gate infidelity. Finally, we demonstrate that low-pass filtering the AC signal used to drive two-qubit gates between the first and second harmonic frequencies can reduce qubit sensitivity to flux noise at the AC sweet spot (ACSS), confirming an earlier theoretical prediction. The framework we present to determine instrumentation noise floors required for high entangling two-qubit gate fidelity should be extensible to other quantum information processing systems.

Demonstration of a Parametrically-Activated Entangling Gate Protected from Flux Noise

  1. Sabrina S. Hong,
  2. Alexander T. Papageorge,
  3. Prasahnt Sivarajah,
  4. Genya Crossman,
  5. Nicolas Dider,
  6. Anthony M. Polloreno,
  7. Eyob A. Sete,
  8. Stefan W. Turkowski,
  9. Marcus P. da Silva,
  10. and Blake R. Johnson
In state-of-the-art quantum computing platforms, including superconducting qubits and trapped ions, imperfections in the 2-qubit entangling gates are the dominant contributions of error
to system-wide performance. Recently, a novel 2-qubit parametric gate was proposed and demonstrated with superconducting transmon qubits. This gate is activated through RF modulation of the transmon frequency and can be operated at an amplitude where the performance is first-order insensitive to flux-noise. In this work we experimentally validate the existence of this AC sweet spot and demonstrate its dependence on white noise power from room temperature electronics. With these factors in place, we measure coherence-limited entangling-gate fidelities as high as 99.2 ± 0.15%.

Manufacturing low dissipation superconducting quantum processors

  1. Ani Nersisyan,
  2. Stefano Poletto,
  3. Nasser Alidoust,
  4. Riccardo Manenti,
  5. Russ Renzas,
  6. Cat-Vu Bui,
  7. Kim Vu,
  8. Tyler Whyland,
  9. Yuvraj Mohan,
  10. Eyob A. Sete,
  11. Sam Stanwyck,
  12. Andrew Bestwick,
  13. and Matthew Reagor
Enabling applications for solid state quantum technology will require systematically reducing noise, particularly dissipation, in these systems. Yet, when multiple decay channels are
present in a system with similar weight, resolution to distinguish relatively small changes is necessary to infer improvements to noise levels. For superconducting qubits, uncontrolled variation of nominal performance makes obtaining such resolution challenging. Here, we approach this problem by investigating specific combinations of previously reported fabrication techniques on the quality of 242 thin film superconducting resonators and qubits. Our results quantify the influence of elementary processes on dissipation at key interfaces. We report that an end-to-end optimization of the manufacturing process that integrates multiple small improvements together can produce an average T¯¯¯¯1=76±13 μs across 24 qubits with the best qubits having T1≥110 μs. Moreover, our analysis places bounds on energy decay rates for three fabrication-related loss channels present in state-of-the-art superconducting qubits. Understanding dissipation through such systematic analysis may pave the way for lower noise solid state quantum computers.