Alternating Bias Assisted Annealing of Amorphous Oxide Tunnel Junctions

  1. David P. Pappas,
  2. Mark Field,
  3. Cameron Kopas,
  4. Joel A. Howard,
  5. Xiqiao Wang,
  6. Ella Lachman,
  7. Lin Zhou,
  8. Jinsu Oh,
  9. Kameshwar Yadavalli,
  10. Eyob A. Sete,
  11. Andrew Bestwick,
  12. Matthew J. Kramer,
  13. and Joshua Y. Mutus
We demonstrate a transformational technique for controllably tuning the electrical properties of fabricated thermally oxidized amorphous aluminum-oxide tunnel junctions. Using conventional
test equipment to apply an alternating bias to a heated tunnel barrier, giant increases in the room temperature resistance, greater than 70%, can be achieved. The rate of resistance change is shown to be strongly temperature-dependent, and is independent of junction size in the sub-micron regime. In order to measure their tunneling properties at mK temperatures, we characterized transmon qubit junctions treated with this alternating-bias assisted annealing (ABAA) technique. The measured frequencies follow the Ambegaokar-Baratoff relation between the shifted resistance and critical current. Further, these studies show a reduction of junction-contributed loss on the order of ≈2×10−6, along with a significant reduction in resonant- and off-resonant-two level system defects when compared to untreated samples. Imaging with high-resolution TEM shows that the barrier is still predominantly amorphous with a more uniform distribution of aluminum coordination across the barrier relative to untreated junctions. This new approach is expected to be widely applicable to a broad range of devices that rely on amorphous aluminum oxide, as well as the many other metal-insulator-metal structures used in modern electronics.

Modular Superconducting Qubit Architecture with a Multi-chip Tunable Coupler

  1. Mark Field,
  2. Angela Q. Chen,
  3. Ben Scharmann,
  4. Eyob A. Sete,
  5. Feyza Oruc,
  6. Kim Vu,
  7. Valentin Kosenko,
  8. Joshua Y. Mutus,
  9. Stefano Poletto,
  10. and Andrew Bestwick
We use a floating tunable coupler to mediate interactions between qubits on separate chips to build a modular architecture. We demonstrate three different designs of multi-chip tunable
couplers using vacuum gap capacitors or superconducting indium bump bonds to connect the coupler to a microwave line on a common substrate and then connect to the qubit on the next chip. We show that the zero-coupling condition between qubits on separate chips can be achieved in each design and that the relaxation rates for the coupler and qubits are not noticeably affected by the extra circuit elements. Finally, we demonstrate two-qubit gate operations with fidelity at the same level as qubits with a tunable coupler on a single chip. Using one or more indium bonds does not degrade qubit coherence or impact the performance of two-qubit gates.

Full control of superconducting qubits with combined on-chip microwave and flux lines

  1. Riccardo Manenti,
  2. Eyob A. Sete,
  3. Angela Q. Chen,
  4. Shobhan Kulshreshtha,
  5. Jen-Hao Yeh,
  6. Feyza Oruc,
  7. Andrew Bestwick,
  8. Mark Field,
  9. Keith Jackson,
  10. and Stefano Poletto
As the field of quantum computing progresses to larger-scale devices, multiplexing will be crucial to scale quantum processors. While multiplexed readout is common practice for superconducting
devices, relatively little work has been reported about the combination of flux and microwave control lines. Here, we present a method to integrate a microwave line and a flux line into a single „XYZ line“. This combined control line allows us to perform fast single-qubit gates as well as to deliver flux signals to the qubits. The measured relaxation times of the qubits are comparable to state-of-art devices employing separate control lines. We benchmark the fidelity of single-qubit gates with randomized benchmarking, achieving a fidelity above 99.5%, and we demonstrate that XYZ lines can in principle be used to run parametric entangling gates.

Entanglement Across Separate Silicon Dies in a Modular Superconducting Qubit Device

  1. Alysson Gold,
  2. JP Paquette,
  3. Anna Stockklauser,
  4. Matthew J. Reagor,
  5. M. Sohaib Alam,
  6. Andrew Bestwick,
  7. Nicolas Didier,
  8. Ani Nersisyan,
  9. Feyza Oruc,
  10. Armin Razavi,
  11. Ben Scharmann,
  12. Eyob A. Sete,
  13. Biswajit Sur,
  14. Davide Venturelli,
  15. Cody James Winkleblack,
  16. Filip Wudarski,
  17. Mike Harburn,
  18. and Chad Rigetti
Assembling future large-scale quantum computers out of smaller, specialized modules promises to simplify a number of formidable science and engineering challenges. One of the primary
challenges in developing a modular architecture is in engineering high fidelity, low-latency quantum interconnects between modules. Here we demonstrate a modular solid state architecture with deterministic inter-module coupling between four physically separate, interchangeable superconducting qubit integrated circuits, achieving two-qubit gate fidelities as high as 99.1±0.5\% and 98.3±0.3\% for iSWAP and CZ entangling gates, respectively. The quality of the inter-module entanglement is further confirmed by a demonstration of Bell-inequality violation for disjoint pairs of entangled qubits across the four separate silicon dies. Having proven out the fundamental building blocks, this work provides the technological foundations for a modular quantum processor: technology which will accelerate near-term experimental efforts and open up new paths to the fault-tolerant era for solid state qubit architectures.

Manufacturing low dissipation superconducting quantum processors

  1. Ani Nersisyan,
  2. Stefano Poletto,
  3. Nasser Alidoust,
  4. Riccardo Manenti,
  5. Russ Renzas,
  6. Cat-Vu Bui,
  7. Kim Vu,
  8. Tyler Whyland,
  9. Yuvraj Mohan,
  10. Eyob A. Sete,
  11. Sam Stanwyck,
  12. Andrew Bestwick,
  13. and Matthew Reagor
Enabling applications for solid state quantum technology will require systematically reducing noise, particularly dissipation, in these systems. Yet, when multiple decay channels are
present in a system with similar weight, resolution to distinguish relatively small changes is necessary to infer improvements to noise levels. For superconducting qubits, uncontrolled variation of nominal performance makes obtaining such resolution challenging. Here, we approach this problem by investigating specific combinations of previously reported fabrication techniques on the quality of 242 thin film superconducting resonators and qubits. Our results quantify the influence of elementary processes on dissipation at key interfaces. We report that an end-to-end optimization of the manufacturing process that integrates multiple small improvements together can produce an average T¯¯¯¯1=76±13 μs across 24 qubits with the best qubits having T1≥110 μs. Moreover, our analysis places bounds on energy decay rates for three fabrication-related loss channels present in state-of-the-art superconducting qubits. Understanding dissipation through such systematic analysis may pave the way for lower noise solid state quantum computers.

Superconducting Through-Silicon Vias for Quantum Integrated Circuits

  1. Mehrnoosh Vahidpour,
  2. William O'Brien,
  3. Jon Tyler Whyland,
  4. Joel Angeles,
  5. Jayss Marshall,
  6. Diego Scarabelli,
  7. Genya Crossman,
  8. Kamal Yadav,
  9. Yuvraj Mohan,
  10. Catvu Bui,
  11. Vijay Rawat,
  12. Russ Renzas,
  13. Nagesh Vodrahalli,
  14. Andrew Bestwick,
  15. and Chad Rigetti
We describe a microfabrication process for superconducting through-silicon vias appropriate for use in superconducting qubit quantum processors. With a sloped-wall via geometry, we
can use non-conformal metal deposition methods such as electron-beam evaporation and sputtering, which reliably deposit high quality superconducting films. Via superconductivity is validated by demonstrating zero via-to-via resistance below the critical temperature of aluminum.

Superconducting Caps for Quantum Integrated Circuits

  1. William O'Brien,
  2. Mehrnoosh Vahidpour,
  3. Jon Tyler Whyland,
  4. Joel Angeles,
  5. Jayss Marshall,
  6. Diego Scarabelli,
  7. Genya Crossman,
  8. Kamal Yadav,
  9. Yuvraj Mohan,
  10. Catvu Bui,
  11. Vijay Rawat,
  12. Russ Renzas,
  13. Nagesh Vodrahalli,
  14. Andrew Bestwick,
  15. and Chad Rigetti
We report on the fabrication and metrology of superconducting caps for qubit circuits. As part of a 3D quantum integrated circuit architecture, a cap chip forms the upper half of an
enclosure that provides isolation, increases vacuum participation ratio, and improves performance of individual resonant elements. Here, we demonstrate that such caps can be reliably fabricated, placed on a circuit chip, and form superconducting connections to the circuit.