Quantum computers will require quantum error correction to reach the low error rates necessary for solving problems that surpass the capabilities of conventional computers. One of thedominant errors limiting the performance of quantum error correction codes across multiple technology platforms is leakage out of the computational subspace arising from the multi-level structure of qubit implementations. Here, we present a resource-efficient universal leakage reduction unit for superconducting qubits using parametric flux modulation. This operation removes leakage down to our measurement accuracy of 7⋅10−4 in approximately 50ns with a low error of 2.5(1)⋅10−3 on the computational subspace, thereby reaching durations and fidelities comparable to those of single-qubit gates. We demonstrate that using the leakage reduction unit in repeated weight-two stabilizer measurements reduces the total number of detected errors in a scalable fashion to close to what can be achieved using leakage-rejection methods which do not scale. Our approach does neither require additional control electronics nor on-chip components and is applicable to both auxiliary and data qubits. These benefits make our method particularly attractive for mitigating leakage in large-scale quantum error correction circuits, a crucial requirement for the practical implementation of fault-tolerant quantum computation.

Three-dimensional device integration facilitates the construction of superconducting quantum information processors with more than several tens of qubits by distributing elements suchas control wires, qubits, and resonators between multiple layers. The frequencies of resonators and qubits in flip-chip-bonded multi-chip modules depend on the details of their electromagnetic environment defined by the conductors and dielectrics in their vicinity. Accurate frequency targeting therefore requires precise control of the separation between chips and minimization of their relative tilt. Here, we describe a method to control the inter-chip separation by using polymer spacers. Compared to an identical process without spacers, we reduce the measured planarity error by a factor of 3.5, to a mean tilt of 76(35) μrad, and the deviation from the target inter-chip separation by a factor of ten, to a mean of 0.4(8) μm. We apply this process to coplanar waveguide resonator samples and observe chip-to-chip resonator frequency variations below 50 MHz (≈ 1 %). We measure internal quality factors of 5×105 at the single-photon level, suggesting that the added spacers are compatible with low-loss device fabrication.

The ability to execute high-fidelity operations is crucial to scaling up quantum devices to large numbers of qubits. However, signal distortions originating from non-linear componentsin the control lines can limit the performance of single-qubit gates. In this work, we use a measurement based on error amplification to characterize and correct the small single-qubit rotation errors originating from the non-linear scaling of the qubit drive rate with the amplitude of the programmed pulse. With our hardware, and for a 15-ns pulse, the rotation angles deviate by up to several degrees from a linear model. Using purity benchmarking, we find that control errors reach 2×10−4, which accounts for half of the total gate error. Using cross-entropy benchmarking, we demonstrate arbitrary-angle single-qubit gates with coherence-limited errors of 2×10−4 and leakage below 6×10−5. While the exact magnitude of these errors is specific to our setup, the presented method is applicable to any source of non-linearity. Our work shows that the non-linearity of qubit drive line components imposes a limit on the fidelity of single-qubit gates, independent of improvements in coherence times, circuit design, or leakage mitigation when not corrected for.

Quantum computing crucially relies on the ability to efficiently characterize the quantum states output by quantum hardware. Conventional methods which probe these states through directmeasurements and classically computed correlations become computationally expensive when increasing the system size. Quantum neural networks tailored to recognize specific features of quantum states by combining unitary operations, measurements and feedforward promise to require fewer measurements and to tolerate errors. Here, we realize a quantum convolutional neural network (QCNN) on a 7-qubit superconducting quantum processor to identify symmetry-protected topological (SPT) phases of a spin model characterized by a non-zero string order parameter. We benchmark the performance of the QCNN based on approximate ground states of a family of cluster-Ising Hamiltonians which we prepare using a hardware-efficient, low-depth state preparation circuit. We find that, despite being composed of finite-fidelity gates itself, the QCNN recognizes the topological phase with higher fidelity than direct measurements of the string order parameter for the prepared states.