Josephson junctions are a key element of superconducting quantum technology, serving as the core building blocks of superconducting qubits. We present an experimental study on room-temperatureelectrical tuning of aluminum junctions, showing that voltage pulses can controllably increase their resistance and adjust the Josephson energy while maintaining qubit quality factors above 1 million. We find that the rate of resistance increase scales exponentially with pulse amplitude during manipulation, after which the spontaneous resistance increase scales proportionally to the amount of manipulation. We show that this spontaneous increase halts at cryogenic temperatures, and resumes again at room temperature. Using our stepwise protocol, we achieve up to a 270% increase in junction resistance, corresponding to a reduction of nearly 2 GHz of the qubit transition frequency. These results establish the achievable range, relaxation behavior, and practical limits of electrical tuning, enabling post-fabrication mitigation of frequency crowding in quantum processors.
The fidelity of operations on a solid-state quantum processor is ultimately bounded by decoherence effects induced by a fluctuating environment. Characterizing environmental fluctuationsis challenging because the acquisition time of experimental protocols limits the precision with which the environment can be measured and may obscure the detailed structure of these fluctuations. Here we present a real-time Bayesian method for estimating the relaxation rate of a qubit, leveraging a classical controller with an integrated field-programmable gate array (FPGA). Using our FPGA-powered Bayesian method, we adaptively and continuously track the relaxation-time fluctuations of two fixed-frequency superconducting transmon qubits, which exhibit average relaxation times of approximately 0.17 ms and occasionally exceed 0.5 ms. Our technique allows for the estimation of these relaxation times in a few milliseconds, more than two orders of magnitude faster than previous nonadaptive methods, and allows us to observe fluctuations up to 5 times the qubit’s average relaxation rates on significantly shorter timescales than previously reported. Our statistical analysis reveals that these fluctuations occur on much faster timescales than previously understood, with two-level-system switching rates reaching up to 10 Hz. Our work offers an appealing solution for rapid relaxation-rate characterization in device screening and for improved understanding of fast relaxation dynamics.
Flux-tunable qubits and couplers are common components in superconducting quantum processors. However, dynamically controlling these elements via current pulses poses challenges dueto distortions and transients in the propagating signals. In particular, long-time transients can persist, adversely affecting subsequent qubit control operations. We model the flux control line as a first-order RC circuit and introduce a class of pulses designed to mitigate long-time transients. We theoretically demonstrate the robustness of these pulses against parameter mischaracterization and provide experimental evidence of their effectiveness in mitigating transients when applied to a flux-tunable qubit coupler. The proposed pulse design offers a practical solution for mitigating long-time transients, enabling efficient and reliable experiment tune-ups without requiring detailed flux line characterization.
It is advantageous for any quantum processor to support different classes of two-qubit quantum logic gates when compiling quantum circuits, a property that is typically not seen withexisting platforms. In particular, access to a gate set that includes support for the CZ-type, the iSWAP-type, and the SWAP-type families of gates, renders conversions between these gate families unnecessary during compilation as any two-qubit Clifford gate can be executed using at most one two-qubit gate from this set, plus additional single-qubit gates. We experimentally demonstrate that a SWAP gate can be decomposed into one iSWAP gate followed by one CZ gate, affirming a more efficient compilation strategy over the conventional approach that relies on three iSWAP or three CZ gates to replace a SWAP gate. Our implementation makes use of a superconducting quantum processor design based on fixed-frequency transmon qubits coupled together by a parametrically modulated tunable transmon coupler, extending this platform’s native gate set so that any two-qubit Clifford unitary matrix can be realized using no more than two two-qubit gates and single-qubit gates.