Achieving high-fidelity operation in large-scale superconducting qubit systems requires not only control hardware with broad frequency coverage, low crosstalk, and tight synchronizationbut also software that coordinates system configuration, experiment execution, and data analysis. Here we present an integrated qubit-control system that combines broadband microwave hardware with a pulse-level software stack for scalable superconducting qubit experiments. The hardware provides broadband microwave coverage, including an instantaneous span of up to 1.6 GHz from a control output, while the software reduces setup and calibration overhead through automated configuration and built-in experiment workflows. We validate the system on a 64-qubit fixed-frequency transmon chip through full-chip frequency identification and representative demonstrations, including multi-unit far-detuned cross-resonance calibration and benchmarking that yields a measured two-qubit gate fidelity of 98.34%, and multilevel readout beyond the computational subspace. By disclosing the hardware architecture and releasing the software stack as open source, this work provides an inspectable hardware-software foundation for scalable superconducting qubit control experiments.
Fixed-frequency transmon qubits, characterized by simple architectures and long coherence times, are promising platforms for large-scale quantum computing. However, the rapidly increasingfrequency collisions, which directly reduce the fabrication yield, hinder scaling, especially in cross-resonance (CR) gate-based architectures, wherein the restricted drive frequency severely limits the available design space. We investigate the Stark-induced ZZ by level excursions (siZZle) gate, which relaxes this limitation by allowing arbitrary drive-frequency choices. Extensive numerical analyses across a broad parameter range — including the far-detuned regime that has received negligible prior attention — reveal wide operating windows that support controlled-Z (CZ) fidelities >99.6%. Leveraging these windows, we design lattice architectures containing >1000 qubits, showing that even under 0.25% fabrication-induced frequency dispersion, the zero-collision yields in square and heavy-hexagonal lattices reach 80% and 100%, respectively. Thus, the siZZle-CZ gate is a scalable and collision-robust alternative to the CR gate, offering a viable route toward high-yield fixed-frequency transmon quantum processors.
This paper proposes a cost-effective architecture for an RF pulse generator for superconducting qubits. Most existing works use arbitrary waveform generators (AWGs) that require botha large amount of high-bandwidth memories and high-performance analog circuits to achieve the highest gate fidelity with an optimized RF pulse waveform. The proposed pulse generator architecture significantly simplifies both the generator circuit and the waveform of the RF pulse to a cost-aware square pulses. This architecture eliminates the requirement for power- and cost-intensive AWG, a major obstacle in realizing scalable quantum computers. Additionally, this paper proposes a process to optimize pulse waveforms to maximize fidelity of gate operations for single and multiple qubits. Quantum dynamics simulation of transmon qubits, wherein the state of system evolves with time, demonstrates that our pulse generator can achieve practically the same gate fidelity as ideal RF pulses, while substantially reducing the performance requirements of memory and analog circuits.