Hidehisa Shiomi

QuBE/Qubex: an integrated hardware-software system for superconducting qubit experiments with broadband control

  1. Akinori Machino,
  2. Kazuhisa Ogawa,
  3. Takefumi Miyoshi,
  4. Hidehisa Shiomi,
  5. Shinichi Morisaka,
  6. Ryo Matsuda,
  7. Nilton F. G. Filho,
  8. Koichiro Ban,
  9. Takafumi Miyanaga,
  10. Keisuke Koike,
  11. Ryutaro Ohira,
  12. Toshi Sumida,
  13. Yoshinori Kurimoto,
  14. Yuuya Sugita,
  15. Yosuke Ito,
  16. Yasunari Suzuki,
  17. Peter A. Spring,
  18. Shiyu Wang,
  19. Hiroto Mukai,
  20. Arvind Mamgain,
  21. Shuhei Tamate,
  22. Yutaka Tabuchi,
  23. Yasunobu Nakamura,
  24. and Makoto Negoro
Achieving high-fidelity operation in large-scale superconducting qubit systems requires not only control hardware with broad frequency coverage, low crosstalk, and tight synchronization
but also software that coordinates system configuration, experiment execution, and data analysis. Here we present an integrated qubit-control system that combines broadband microwave hardware with a pulse-level software stack for scalable superconducting qubit experiments. The hardware provides broadband microwave coverage, including an instantaneous span of up to 1.6 GHz from a control output, while the software reduces setup and calibration overhead through automated configuration and built-in experiment workflows. We validate the system on a 64-qubit fixed-frequency transmon chip through full-chip frequency identification and representative demonstrations, including multi-unit far-detuned cross-resonance calibration and benchmarking that yields a measured two-qubit gate fidelity of 98.34%, and multilevel readout beyond the computational subspace. By disclosing the hardware architecture and releasing the software stack as open source, this work provides an inspectable hardware-software foundation for scalable superconducting qubit control experiments.
arxiv pdf

SPulseGen: Succinct pulse generator architecture maximizing gate fidelity for superconducting quantum computers

  1. Ryosuke Matsuo,
  2. Kazuhisa Ogawa,
  3. Hidehisa Shiomi,
  4. Makoto Negoro,
  5. Takefumi Miyoshi,
  6. Michihiro Shintani,
  7. Hiromitsu Awano,
  8. Takashi Sato,
  9. and Jun Shiomi
This paper proposes a cost-effective architecture for an RF pulse generator for superconducting qubits. Most existing works use arbitrary waveform generators (AWGs) that require both
a large amount of high-bandwidth memories and high-performance analog circuits to achieve the highest gate fidelity with an optimized RF pulse waveform. The proposed pulse generator architecture significantly simplifies both the generator circuit and the waveform of the RF pulse to a cost-aware square pulses. This architecture eliminates the requirement for power- and cost-intensive AWG, a major obstacle in realizing scalable quantum computers. Additionally, this paper proposes a process to optimize pulse waveforms to maximize fidelity of gate operations for single and multiple qubits. Quantum dynamics simulation of transmon qubits, wherein the state of system evolves with time, demonstrates that our pulse generator can achieve practically the same gate fidelity as ideal RF pulses, while substantially reducing the performance requirements of memory and analog circuits.
arxiv pdf