As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity.Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo > 40 {\mu}s) in the presence of silicon posts as near as 350 {\mu}m to the qubit.
Superconducting quantum computing architectures comprise resonators and qubits that experience energy loss due to two-level systems (TLS) in bulk and interfacial dielectrics. Understandingthese losses is critical to improving performance in superconducting circuits. In this work, we present a method for quantifying the TLS losses of different bulk and interfacial dielectrics present in superconducting coplanar waveguide (CPW) resonators. By combining statistical characterization of sets of specifically designed CPW resonators on isotropically etched silicon substrates with detailed electromagnetic modeling, we determine the separate loss contributions from individual material interfaces and bulk dielectrics. This technique for analyzing interfacial TLS losses can be used to guide targeted improvements to qubits, resonators, and their superconducting fabrication processes.
Improving the performance of superconducting qubits and resonators generally results from a combination of materials and fabrication process improvements and design modifications thatreduce device sensitivity to residual losses. One instance of this approach is to use trenching into the device substrate in combination with superconductors and dielectrics with low intrinsic losses to improve quality factors and coherence times. Here we demonstrate titanium nitride coplanar waveguide resonators with mean quality factors exceeding two million and controlled trenching reaching 2.2 μm into the silicon substrate. Additionally, we measure sets of resonators with a range of sizes and trench depths and compare these results with finite-element simulations to demonstrate quantitative agreement with a model of interface dielectric loss. We then apply this analysis to determine the extent to which trenching can improve resonator performance.
Quantum annealing is an optimization technique which potentially leverages quantum tunneling to enhance computational performance. Existing quantum annealers use superconducting fluxqubits with short coherence times, limited primarily by the use of large persistent currents Ip. Here, we examine an alternative approach, using qubits with smaller Ip and longer coherence times. We demonstrate tunable coupling, a basic building block for quantum annealing, between two flux qubits with small (∼50 nA) persistent currents. Furthermore, we characterize qubit coherence as a function of coupler setting and investigate the effect of flux noise in the coupler loop on qubit coherence. Our results provide insight into the available design space for next-generation quantum annealers with improved coherence.