Rabi Das

Solid-state qubits integrated with superconducting through-silicon vias

  1. Donna-Ruth W. Yost,
  2. Mollie E. Schwartz,
  3. Justin Mallek,
  4. Danna Rosenberg,
  5. Corey Stull,
  6. Jonilyn L. Yoder,
  7. Greg Calusine,
  8. Matt Cook,
  9. Rabi Das,
  10. Alexandra L. Day,
  11. Evan B. Golden,
  12. David K. Kim,
  13. Alexander Melville,
  14. Bethany M. Niedzielski,
  15. Wayne Woods,
  16. Andrew J. Kerman,
  17. and Willam D. Oliver
As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require,
access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays — provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs — 10 μm wide by 20 μm long by 200 μm deep — with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
arxiv pdf

Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits

  1. Bethany M. Niedzielski,
  2. David K. Kim,
  3. Mollie E. Schwartz,
  4. Danna Rosenberg,
  5. Greg Calusine,
  6. Rabi Das,
  7. Alexander J. Melville,
  8. Jason Plant,
  9. Livia Racz,
  10. Jonilyn L. Yoder,
  11. Donna Ruth-Yost,
  12. and William D. Oliver
As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips will become necessary to enable increased density and connectivity.
Precise control of the spacing between these chips is required for accurate prediction of circuit performance. In this paper, we demonstrate an improvement in the planarity of bonded superconducting qubit chips while retaining device performance by utilizing hard-stop silicon spacer posts. These silicon spacers are defined by etching several microns into a silicon substrate and are compatible with 3D-integrated qubit fabrication. This includes fabrication of Josephson junctions, superconducting air-bridge crossovers, underbump metallization and indium bumps. To qualify the integrated process, we demonstrate high-quality factor resonators on the etched surface and measure qubit coherence (T1, T2,echo > 40 {\mu}s) in the presence of silicon posts as near as 350 {\mu}m to the qubit.
arxiv pdf