Reducing leakage of single-qubit gates for superconducting quantum processors using analytical control pulse envelopes

  1. Eric Hyyppä,
  2. Antti Vepsäläinen,
  3. Miha Papič,
  4. Chun Fai Chan,
  5. Sinan Inel,
  6. Alessandro Landra,
  7. Wei Liu,
  8. Jürgen Luus,
  9. Fabian Marxer,
  10. Caspar Ockeloen-Korppi,
  11. Sebastian Orbell,
  12. Brian Tarasinski,
  13. and Johannes Heinsoo
Improving the speed and fidelity of quantum logic gates is essential to reach quantum advantage with future quantum computers. However, fast logic gates lead to increased leakage errors
in superconducting quantum processors based on qubits with low anharmonicity, such as transmons. To reduce leakage errors, we propose and experimentally demonstrate two new analytical methods, Fourier ansatz spectrum tuning derivative removal by adiabatic gate (FAST DRAG) and higher-derivative (HD) DRAG, both of which enable shaping single-qubit control pulses in the frequency domain to achieve stronger suppression of leakage transitions compared to previously demonstrated pulse shapes. Using the new methods to suppress the ef-transition of a transmon qubit with an anharmonicity of -212 MHz, we implement RX(π/2)-gates with a leakage error below 3.0×10−5 down to a gate duration of 6.25 ns, which corresponds to a 20-fold reduction in leakage compared to a conventional Cosine DRAG pulse. Employing the FAST DRAG method, we further achieve an error per gate of (1.56±0.07)×10−4 at a 7.9-ns gate duration, outperforming conventional pulse shapes both in terms of error and gate speed. Furthermore, we study error-amplifying measurements for the characterization of temporal microwave control pulse distortions, and demonstrate that non-Markovian coherent errors caused by such distortions may be a significant source of error for sub-10-ns single-qubit gates unless corrected using predistortion.

Charge-parity switching effects and optimisation of transmon-qubit design parameters

  1. Miha Papič,
  2. Jani Tuorila,
  3. Adrian Auer,
  4. Inés de Vega,
  5. and Amin Hosseinkhani
Enhancing the performance of noisy quantum processors requires improving our understanding of error mechanisms and the ways to overcome them. A judicious selection of qubit design parameters,
guided by an accurate error model, plays a pivotal role in improving the performance of quantum processors. In this study, we identify optimal ranges for qubit design parameters, grounded in comprehensive noise modeling. To this end, we commence by analyzing a previously unexplored error mechanism that can perturb diabatic two-qubit gates due to charge-parity switches caused by quasiparticles. We show that such charge-parity switching can be the dominant quasiparticle-related error source in a controlled-Z gate between two qubits. Moreover, we also demonstrate that quasiparticle dynamics, resulting in uncontrolled charge-parity switches, induce a residual longitudinal interaction between qubits in a tunable-coupler circuit. Our analysis of optimal design parameters is based on a performance metric for quantum circuit execution that takes into account the fidelity and frequencies of the appearance of both single and two-qubit gates in the circuit. This performance metric together with a detailed noise model enables us to find an optimal range for the qubit design parameters. Substantiating our findings through exact numerical simulations, we establish that fabricating quantum chips within this optimal parameter range not only augments the performance metric but also ensures its continued improvement with the enhancement of individual qubit coherence properties. Conversely, straying from the optimal parameter range can lead to the saturation of the performance metric. Our systematic analysis offers insights and serves as a guiding framework for the development of the next generation of transmon-based quantum processors.

Error Sources of Quantum Gates in Superconducting Qubits

  1. Miha Papič,
  2. Adrian Auer,
  3. and Inés de Vega
As transmon based superconducting qubit architectures are one of the most promising candidates for the realization of large-scale quantum computation, it is crucial to know what are
the main sources of the error in the implemented quantum gates. In this work we make a realistic assessment of the contributions of physical error sources to the infidelities of both single and two-qubit gates, where we focus on the non-adiabatic implementation of the CZ gate with tunable couplers. We consider all relevant noise sources, including non-Markovian noise, electronics imperfections and the effect of tunable couplers to the error of the computation. Furthermore, we provide a learning based framework that allows to extract the contribution of each noise source to the infidelity of a series of gates with a small number of experimental measurements.

Long-distance transmon coupler with CZ gate fidelity above 99.8%

  1. Fabian Marxer,
  2. Antti Vepsäläinen,
  3. Shan W. Jolin,
  4. Jani Tuorila,
  5. Alessandro Landra,
  6. Caspar Ockeloen-Korppi,
  7. Wei Liu,
  8. Olli Ahonen,
  9. Adrian Auer,
  10. Lucien Belzane,
  11. Ville Bergholm,
  12. Chun Fai Chan,
  13. Kok Wai Chan,
  14. Tuukka Hiltunen,
  15. Juho Hotari,
  16. Eric Hyyppä,
  17. Joni Ikonen,
  18. David Janzso,
  19. Miikka Koistinen,
  20. Janne Kotilahti,
  21. Tianyi Li,
  22. Jyrgen Luus,
  23. Miha Papic,
  24. Matti Partanen,
  25. Jukka Räbinä,
  26. Jari Rosti,
  27. Mykhailo Savytskyi,
  28. Marko Seppälä,
  29. Vasilii Sevriuk,
  30. Eelis Takala,
  31. Brian Tarasinski,
  32. Manish J. Thapa,
  33. Francesca Tosto,
  34. Natalia Vorobeva,
  35. Liuqi Yu,
  36. Kuan Yen Tan,
  37. Juha Hassel,
  38. Mikko Möttönen,
  39. and Johannes Heinsoo
Tunable coupling of superconducting qubits has been widely studied due to its importance for isolated gate operations in scalable quantum processor architectures. Here, we demonstrate
a tunable qubit-qubit coupler based on a floating transmon device which allows us to place qubits at least 2 mm apart from each other while maintaining over 50 MHz coupling between the coupler and the qubits. In the introduced tunable-coupler design, both the qubit-qubit and the qubit-coupler couplings are mediated by two waveguides instead of relying on direct capacitive couplings between the components, reducing the impact of the qubit-qubit distance on the couplings. This leaves space for each qubit to have an individual readout resonator and a Purcell filter needed for fast high-fidelity readout. In addition, the large qubit-qubit distance reduces unwanted non-nearest neighbor coupling and allows multiple control lines to cross over the structure with minimal crosstalk. Using the proposed flexible and scalable architecture, we demonstrate a controlled-Z gate with (99.81±0.02)% fidelity.