Evan B. Golden

Fabrication and Properties of NbN/NbNx/NbN and Nb/NbNx/Nb Josephson Junctions

  1. Sergey K. Tolpygo,
  2. Ravi Rastogi,
  3. David Kim,
  4. Terence J. Weir,
  5. Neel Parmar,
  6. and Evan B. Golden
Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs.
We have been developing a ten-superconductor-layer planarized fabrication process with NbN kinetic inductors and searching for suitable self-shunted JJs to potentially replace high Josephson critical current density, Jc, Nb/Al-AlOx/Nb junctions. We report on the fabrication and electrical properties of NbN/NbNx/NbN junctions produced by reactive sputtering in Ar+N2 mixture on 200-mm wafers at 200 oC and incorporated into a planarized process with two Nb ground planes and Nb wiring layer. Here NbN is a stoichiometric nitride with superconducting critical temperature Tc =15 K and NbNx is a high resistivity, nonsuperconducting nitride deposited using a higher nitrogen partial pressure than for the NbN electrodes. For comparison, we co-fabricated Nb/NbNx/Nb JJs using the same NbNx barriers deposited at 20 oC. We varied the NbNx barrier thickness from 5 nm to 20 nm, resulting in the range of Jc from about 1 mA/um^2 down to ~10 uA/um^2, and extracted coherence length of 3 nm and 4 nm in NbNx deposited, respectively at 20 oC and 200 oC. Both types of JJs are well described by resistively and capacitively shunted junction model without any excess current. We found the Jc of NbN/NbNx/NbN JJs to be somewhat lower than of Nb/NbNx/Nb JJs with the same barrier thickness, despite a much higher Tc and energy gap of NbN than of Nb electrodes. IcRn products up to ~ 0.5 mV were obtained for JJs with Jc~ 0.6 mA/um^2. Jc(T) dependences have been measured.
arxiv pdf

Solid-state qubits integrated with superconducting through-silicon vias

  1. Donna-Ruth W. Yost,
  2. Mollie E. Schwartz,
  3. Justin Mallek,
  4. Danna Rosenberg,
  5. Corey Stull,
  6. Jonilyn L. Yoder,
  7. Greg Calusine,
  8. Matt Cook,
  9. Rabi Das,
  10. Alexandra L. Day,
  11. Evan B. Golden,
  12. David K. Kim,
  13. Alexander Melville,
  14. Bethany M. Niedzielski,
  15. Wayne Woods,
  16. Andrew J. Kerman,
  17. and Willam D. Oliver
As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require,
access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays — provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs — 10 μm wide by 20 μm long by 200 μm deep — with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
arxiv pdf