Neel Parmar

Elimination of Flux Trapping in Superconducting Circuits in Ambient Magnetic Fields

  1. Rohan T. Kapur,
  2. Alex Wynn,
  3. Sergey K. Tolpygo,
  4. Neel Parmar,
  5. Anil Mankame,
  6. Adam A. Libson,
  7. Rabindra Das,
  8. Michele Kelley,
  9. Pauli Kehayias,
  10. Nathaniel J. O'Connor,
  11. Collin N. Muniz,
  12. Justin L. Mallek,
  13. and Jennifer M. Schloss
Superconductor digital electronics and quantum computing with superconducting qubits are promising next-generation computing technologies. When cooled down or operated in the presence
of a nonzero background magnetic field Br, superconducting thin films comprising the circuits can trap magnetic vortices that can degrade circuit or qubit performance. In this work, we report a practical solution for eliminating flux trapped during cooldown in ambient magnetic fields, Br≤60 $\upmu$T, based on controlled local thermal gradients and moats, etched holes in the superconducting films of the circuit. Thermal gradients created by integrated on-chip resistive heaters move vortices towards the moats, where they become trapped away from circuitry regions and pinning sites. Using magnetic imaging and electrical circuit readout, we demonstrate that this approach is capable of removing magnetic flux trapped during field cooling and magnetic flux nucleated by circuit operation. If used in an environment with basic magnetic shielding, this solution is capable of suppressing all magnetic flux in a large-scale circuit, overcoming one of the long-standing challenges preventing high-performance scalable computing using superconductors.
arxiv pdf

Fabrication and Properties of NbN/NbNx/NbN and Nb/NbNx/Nb Josephson Junctions

  1. Sergey K. Tolpygo,
  2. Ravi Rastogi,
  3. David Kim,
  4. Terence J. Weir,
  5. Neel Parmar,
  6. and Evan B. Golden
Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs.
We have been developing a ten-superconductor-layer planarized fabrication process with NbN kinetic inductors and searching for suitable self-shunted JJs to potentially replace high Josephson critical current density, Jc, Nb/Al-AlOx/Nb junctions. We report on the fabrication and electrical properties of NbN/NbNx/NbN junctions produced by reactive sputtering in Ar+N2 mixture on 200-mm wafers at 200 oC and incorporated into a planarized process with two Nb ground planes and Nb wiring layer. Here NbN is a stoichiometric nitride with superconducting critical temperature Tc =15 K and NbNx is a high resistivity, nonsuperconducting nitride deposited using a higher nitrogen partial pressure than for the NbN electrodes. For comparison, we co-fabricated Nb/NbNx/Nb JJs using the same NbNx barriers deposited at 20 oC. We varied the NbNx barrier thickness from 5 nm to 20 nm, resulting in the range of Jc from about 1 mA/um^2 down to ~10 uA/um^2, and extracted coherence length of 3 nm and 4 nm in NbNx deposited, respectively at 20 oC and 200 oC. Both types of JJs are well described by resistively and capacitively shunted junction model without any excess current. We found the Jc of NbN/NbNx/NbN JJs to be somewhat lower than of Nb/NbNx/Nb JJs with the same barrier thickness, despite a much higher Tc and energy gap of NbN than of Nb electrodes. IcRn products up to ~ 0.5 mV were obtained for JJs with Jc~ 0.6 mA/um^2. Jc(T) dependences have been measured.
arxiv pdf