Xinfang Zhang

Quantitative Rules for Parallel Calibration and Drift-Resilient Maintenance of Large-Scale Superconducting Quantum Processors

  1. Zhihao Wu,
  2. Kechengqi Zhu,
  3. Shichuan Xue,
  4. Xinfang Zhang,
  5. Zhaohua Yang,
  6. Zhida Zhang,
  7. Shun Hu,
  8. Cong Li,
  9. Dingdong Liu,
  10. Kangding Zhao,
  11. Peng Luo,
  12. Lingling Lao,
  13. Xiang Fu,
  14. Mingtang Deng,
  15. Junjie Wu,
  16. and Kai Lu
As superconducting quantum processors scale toward hundreds of qubits, manual calibration becomes increasingly costly and difficult to sustain. Here we address two system-level factors
governing automated calibration, namely, crosstalk induced by parallel operations and temporal drift of control parameters. On a 66-qubit superconducting processor, cross-entropy benchmarking shows that single-qubit calibration tolerates full-chip concurrency with minimal fidelity loss, whereas CZ calibration requires a minimum coupler-graph distance of four to avoid elevated control errors. Continuous monitoring of representative qubit and coupler parameters further yields quantitative refresh rules that assign refresh priority by error-budget consumption. These results turn two conventionally heuristic choices, the concurrency density of calibration tasks and the refresh priority of each control parameter, into measurable operating rules. Implemented within an automated calibration framework, the rules support a six-qubit Greenberger-Horne-Zeilinger state with a zero-noise-extrapolated fidelity of 89.64%, distance-dependent logical-error suppression in a single-cycle repetition-code benchmark, and a reduction of the mean single-qubit error from 0.023 to 0.011 on a 337-qubit processor, providing an experimentally grounded reference for the automated calibration and maintenance of current and future large-scale superconducting quantum systems.
arxiv pdf

Lifting connectivity bottlenecks in superconducting quantum processors via enriched native two-qubit gates

  1. Hanyi Wang,
  2. Jingzhe Guo,
  3. Lijun Sun,
  4. Zhaohui Yang,
  5. Weizhi Tao,
  6. Xingye Yuan,
  7. Qiankun Wang,
  8. Bihao Guo,
  9. Chunwang Liu,
  10. Rui Yang,
  11. Yang Li,
  12. Yu Fan,
  13. Jiasheng Hu,
  14. Junhe Wang,
  15. Shuyue Zheng,
  16. Shengbin Wang,
  17. Xinfang Zhang,
  18. Feng Wu,
  19. Hantao Sun,
  20. and Jianxin Chen
Limited qubit connectivity is a central architectural constraint in superconducting quantum processors, whose planar layouts require additional gates to mediate interactions between
distant qubits. Here, we use the AshN control scheme, where rich two-qubit control on every nearest-neighbour pair allows a logical interaction and the required qubit routing to be merged into a single native operation, effectively transforming a sparse hardware graph into a more connected computational architecture. For the benchmark instances studied, the resulting synthesis capability enables reliable execution on constrained one- and two-dimensional lattices, with compiled two-qubit gate counts approaching those of an all-to-all-connected reference. Across seven benchmark circuits on one- and two-dimensional topologies, the AshN-based implementation achieves geometric-mean reductions of 45.2% and 43.7% in two-qubit gate count compared with controlled-Z-based compilation, respectively. Using AshN gates, we prepare an eight-qubit two-excitation Dicke state with a fidelity of 0.736 and certify its genuine multipartite entanglement using a fully positive-partial-transpose witness, whereas the same witness does not certify entanglement for the CZ-based implementation. The state fidelity and entanglement certification remain robust across the tested lattice configurations, including those with up to three connectivity defects. Our work establishes native-gate engineering as a practical approach to mitigating connectivity constraints.
arxiv pdf