Lifting connectivity bottlenecks in superconducting quantum processors via enriched native two-qubit gates

  1. Hanyi Wang,
  2. Jingzhe Guo,
  3. Lijun Sun,
  4. Zhaohui Yang,
  5. Weizhi Tao,
  6. Xingye Yuan,
  7. Qiankun Wang,
  8. Bihao Guo,
  9. Chunwang Liu,
  10. Rui Yang,
  11. Yang Li,
  12. Yu Fan,
  13. Jiasheng Hu,
  14. Junhe Wang,
  15. Shuyue Zheng,
  16. Shengbin Wang,
  17. Xinfang Zhang,
  18. Feng Wu,
  19. Hantao Sun,
  20. and Jianxin Chen
Limited qubit connectivity is a central architectural constraint in superconducting quantum processors, whose planar layouts require additional gates to mediate interactions between
distant qubits. Here, we use the AshN control scheme, where rich two-qubit control on every nearest-neighbour pair allows a logical interaction and the required qubit routing to be merged into a single native operation, effectively transforming a sparse hardware graph into a more connected computational architecture. For the benchmark instances studied, the resulting synthesis capability enables reliable execution on constrained one- and two-dimensional lattices, with compiled two-qubit gate counts approaching those of an all-to-all-connected reference. Across seven benchmark circuits on one- and two-dimensional topologies, the AshN-based implementation achieves geometric-mean reductions of 45.2% and 43.7% in two-qubit gate count compared with controlled-Z-based compilation, respectively. Using AshN gates, we prepare an eight-qubit two-excitation Dicke state with a fidelity of 0.736 and certify its genuine multipartite entanglement using a fully positive-partial-transpose witness, whereas the same witness does not certify entanglement for the CZ-based implementation. The state fidelity and entanglement certification remain robust across the tested lattice configurations, including those with up to three connectivity defects. Our work establishes native-gate engineering as a practical approach to mitigating connectivity constraints.

SurgeQ: A Hybrid Framework for Ultra-Fast Quantum Processor Design and Crosstalk-Aware Circuit Execution

  1. Xinxuan Chen,
  2. Hongxiang Zhu,
  3. Zhaohui Yang,
  4. Zhaofeng Su,
  5. Jianxin Chen,
  6. Feng Wu,
  7. and Hui-Hai Zhao
Executing quantum circuits on superconducting platforms requires balancing the trade-off between gate errors and crosstalk. To address this, we introduce SurgeQ, a hardware-software
co-design strategy consisting of a design phase and an execution phase, to achieve accelerated circuit execution and improve overall program fidelity. SurgeQ employs coupling-strengthened, faster two-qubit gates while mitigating their increased crosstalk through a tailored scheduling strategy. With detailed consideration of composite noise models, we establish a systematic evaluation pipeline to identify the optimal coupling strength. Evaluations on a comprehensive suite of real-world benchmarks show that SurgeQ generally achieves higher fidelity than up-to-date baselines, and remains effective in combating exponential fidelity decay, achieving up to a million-fold improvement in large-scale circuits.