A critical challenge in developing scalable error-corrected quantum systems is the accumulation of errors while performing operations and measurements. One promising approach is todesign a system where errors can be detected and converted into erasures. A recent proposal aims to do this using a dual-rail encoding with superconducting cavities. In this work, we implement such a dual-rail cavity qubit and use it to demonstrate a projective logical measurement with erasure detection. We measure logical state preparation and measurement errors at the 0.01%-level and detect over 99% of cavity decay events as erasures. We use the precision of this new measurement protocol to distinguish different types of errors in this system, finding that while decay errors occur with probability ∼0.2% per microsecond, phase errors occur 6 times less frequently and bit flips occur at least 170 times less frequently. These findings represent the first confirmation of the expected error hierarchy necessary to concatenate dual-rail erasure qubits into a highly efficient erasure code.
The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computations. To this end, we introducethe circuit-QED dual-rail qubit in which our physical qubit is encoded in the single-photon subspace of two superconducting cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers completely new capabilities. Using a single transmon ancilla, we describe a universal gate set that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors due to the cavity and transmon in all of these operations can be detected and converted to erasure errors, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit delivers an optimal hierarchy of errors and rates, and is expected to be well below the relevant QEC thresholds with today’s devices.
Bosonic quantum error correction has proven to be a successful approach for extending the coherence of quantum memories, but to execute deep quantum circuits, high-fidelity gates betweenencoded qubits are needed. To that end, we present a family of error-detectable two-qubit gates for a variety of bosonic encodings. From a new geometric framework based on a „Bloch sphere“ of bosonic operators, we construct ZZL(θ) and eSWAP(θ) gates for the binomial, 4-legged cat, dual-rail and several other bosonic codes. The gate Hamiltonian is simple to engineer, requiring only a programmable beamsplitter between two bosonic qubits and an ancilla dispersively coupled to one qubit. This Hamiltonian can be realized in circuit QED hardware with ancilla transmons and microwave cavities. The proposed theoretical framework was developed for circuit QED but is generalizable to any platform that can effectively generate this Hamiltonian. Crucially, one can also detect first-order errors in the ancilla and the bosonic qubits during the gates. We show that this allows one to reach error-detected gate fidelities at the 10−4 level with today’s hardware, limited only by second-order hardware errors.
Control electronics for superconducting quantum processors have strict requirements for accurate command of the sensitive quantum states of their qubits. Hinging on the purity of ultra-phase-stableoscillators to upconvert very-low-noise baseband pulses, conventional control systems can become prohibitively complex and expensive when scaling to larger quantum devices, especially as high sampling rates become desirable for fine-grained pulse shaping. Few-GHz radio-frequency digital-to-analog converters (RF DACs) present a more economical avenue for high-fidelity control while simultaneously providing greater command over the spectrum of the synthesized signal. Modern RF DACs with extra-wide bandwidths are able to directly synthesize tones above their sampling rates, thereby keeping the system clock rate at a level compatible with modern digital logic systems while still being able to generate high-frequency pulses with arbitrary profiles. We have incorporated custom superconducting qubit control logic into off-the-shelf hardware capable of low-noise pulse synthesis up to 7.5 GHz using an RF DAC clocked at 5 GHz. Our approach enables highly linear and stable microwave synthesis over a wide bandwidth, giving rise to resource-efficient control and the potential for reducing the required number of cables entering the cryogenic environment. We characterize the performance of the hardware using a five-transmon superconducting device and demonstrate consistently reduced two-qubit gate error (as low as 1.8%) accompanied by superior control chain linearity compared to traditional configurations. The exceptional flexibility and stability further establish a foundation for scalable quantum control beyond intermediate-scale devices.