Bias-preserving and error-detectable entangling operations in a superconducting dual-rail system

  1. Nitish Mehta,
  2. James D. Teoh,
  3. Taewan Noh,
  4. Ankur Agrawal,
  5. Richard Chamberlain,
  6. Tzu-Chiao Chien,
  7. Jacob C. Curtis,
  8. Bassel Heiba Elfeky,
  9. S. M. Farzaneh,
  10. Benjamin Gudlewski,
  11. Trevor Keen,
  12. Nishaad Khedkar,
  13. Cihan Kurter,
  14. Richard Li,
  15. Gangqiang Liu,
  16. Pinlei Lu,
  17. Heather McCarrick,
  18. Anirudh Narla,
  19. Sitakanta Satapathy,
  20. Tali Shemma,
  21. Ruby A. Shi,
  22. Daniel K. Weiss,
  23. Jose Aumentado,
  24. Chan U Lei,
  25. Joseph O. Yuan,
  26. Shantanu O. Mundhada,
  27. S. Harvey Moseley Jr.,
  28. Kevin S. Chou,
  29. and Robert J. Schoelkopf
For useful quantum computation, error-corrected machines are required that can dramatically reduce the inevitable errors experienced by physical qubits. While significant progress has
been made in approaching and exceeding the surface-code threshold in superconducting platforms, large gains in the logical error rate with increasing system size remain out of reach. This is due both to the large number of required physical qubits and the need to operate far below threshold. Importantly, by exploiting the biases and structure of the physical errors, this threshold can be raised. Erasure qubits achieve this by detecting certain errors at the hardware level. Dual-rail qubits encoded in superconducting cavities are a promising erasure qubit wherein the dominant error, photon loss, can be detected and converted to an erasure. In these approaches, the complete set of operations, including two qubit gates, must be high performance and preserve as much of the desirable hierarchy or bias in the errors as possible. Here, we design and realize a novel two-qubit gate for dual-rail erasure qubits based on superconducting microwave cavities. The gate is high-speed (∼500 ns duration), and yields a residual gate infidelity after error detection below 0.1%. Moreover, we experimentally demonstrate that this gate largely preserves the favorable error structure of idling dual-rail qubits, making it ideal for error correction. We measure low erasure rates of ∼0.5% per gate, as well as low and asymmetric dephasing errors that occur at least three times more frequently on control qubits compared to target qubits. Bit-flip errors are practically nonexistent, bounded at the few parts per million level. This error asymmetry has not been well explored but is extremely useful in quantum error correction and flag-qubit contexts, where it can create a faster path to effective error-corrected systems.

Demonstrating a superconducting dual-rail cavity qubit with erasure-detected logical measurements

  1. Kevin S. Chou,
  2. Tali Shemma,
  3. Heather McCarrick,
  4. Tzu-Chiao Chien,
  5. James D. Teoh,
  6. Patrick Winkel,
  7. Amos Anderson,
  8. Jonathan Chen,
  9. Jacob Curtis,
  10. Stijn J. de Graaf,
  11. John W.O. Garmon,
  12. Benjamin Gudlewski,
  13. William D. Kalfus,
  14. Trevor Keen,
  15. Nishaad Khedkar,
  16. Chan U Lei,
  17. Gangqiang Liu,
  18. Pinlei Lu,
  19. Yao Lu,
  20. Aniket Maiti,
  21. Luke Mastalli-Kelly,
  22. Nitish Mehta,
  23. Shantanu O. Mundhada,
  24. Anirudh Narla,
  25. Taewan Noh,
  26. Takahiro Tsunoda,
  27. Sophia H. Xue,
  28. Joseph O. Yuan,
  29. Luigi Frunzio,
  30. Jose Aumentado,
  31. Shruti Puri,
  32. Steven M. Girvin,
  33. S. Harvey Moseley Jr.,
  34. and Robert J. Schoelkopf
A critical challenge in developing scalable error-corrected quantum systems is the accumulation of errors while performing operations and measurements. One promising approach is to
design a system where errors can be detected and converted into erasures. A recent proposal aims to do this using a dual-rail encoding with superconducting cavities. In this work, we implement such a dual-rail cavity qubit and use it to demonstrate a projective logical measurement with erasure detection. We measure logical state preparation and measurement errors at the 0.01%-level and detect over 99% of cavity decay events as erasures. We use the precision of this new measurement protocol to distinguish different types of errors in this system, finding that while decay errors occur with probability ∼0.2% per microsecond, phase errors occur 6 times less frequently and bit flips occur at least 170 times less frequently. These findings represent the first confirmation of the expected error hierarchy necessary to concatenate dual-rail erasure qubits into a highly efficient erasure code.