A mid-circuit erasure check on a dual-rail cavity qubit using the joint-photon number-splitting regime of circuit QED

  1. Stijn J. de Graaf,
  2. Sophia H. Xue,
  3. Benjamin J. Chapman,
  4. James D. Teoh,
  5. Takahiro Tsunoda,
  6. Patrick Winkel,
  7. John W.O. Garmon,
  8. Kathleen M. Chang,
  9. Luigi Frunzio,
  10. Shruti Puri,
  11. and Robert J. Schoelkopf
Quantum control of a linear oscillator using a static dispersive coupling to a nonlinear ancilla underpins a wide variety of experiments in circuit QED. Extending this control to more
than one oscillator while minimizing the required connectivity to the ancilla would enable hardware-efficient multi-mode entanglement and measurements. We show that the spectrum of an ancilla statically coupled to a single mode can be made to depend on the joint photon number in two modes by applying a strong parametric beamsplitter coupling between them. This `joint-photon number-splitting‘ regime extends single-oscillator techniques to two-oscillator control, which we use to realize a hardware-efficient erasure check for a dual-rail qubit encoded in two superconducting cavities. By leveraging the beamsplitter coupling already required for single-qubit gates, this scheme permits minimal connectivity between circuit elements. Furthermore, the flexibility to choose the pulse shape allows us to limit the susceptibility to different error channels. We use this scheme to detect leakage errors with a missed erasure fraction of (9.0±0.5)×10−4, while incurring an erasure rate of 2.92±0.01% and a Pauli error rate of 0.31±0.01%, both of which are dominated by cavity errors.

Demonstrating a superconducting dual-rail cavity qubit with erasure-detected logical measurements

  1. Kevin S. Chou,
  2. Tali Shemma,
  3. Heather McCarrick,
  4. Tzu-Chiao Chien,
  5. James D. Teoh,
  6. Patrick Winkel,
  7. Amos Anderson,
  8. Jonathan Chen,
  9. Jacob Curtis,
  10. Stijn J. de Graaf,
  11. John W.O. Garmon,
  12. Benjamin Gudlewski,
  13. William D. Kalfus,
  14. Trevor Keen,
  15. Nishaad Khedkar,
  16. Chan U Lei,
  17. Gangqiang Liu,
  18. Pinlei Lu,
  19. Yao Lu,
  20. Aniket Maiti,
  21. Luke Mastalli-Kelly,
  22. Nitish Mehta,
  23. Shantanu O. Mundhada,
  24. Anirudh Narla,
  25. Taewan Noh,
  26. Takahiro Tsunoda,
  27. Sophia H. Xue,
  28. Joseph O. Yuan,
  29. Luigi Frunzio,
  30. Jose Aumentado,
  31. Shruti Puri,
  32. Steven M. Girvin,
  33. S. Harvey Moseley Jr.,
  34. and Robert J. Schoelkopf
A critical challenge in developing scalable error-corrected quantum systems is the accumulation of errors while performing operations and measurements. One promising approach is to
design a system where errors can be detected and converted into erasures. A recent proposal aims to do this using a dual-rail encoding with superconducting cavities. In this work, we implement such a dual-rail cavity qubit and use it to demonstrate a projective logical measurement with erasure detection. We measure logical state preparation and measurement errors at the 0.01%-level and detect over 99% of cavity decay events as erasures. We use the precision of this new measurement protocol to distinguish different types of errors in this system, finding that while decay errors occur with probability ∼0.2% per microsecond, phase errors occur 6 times less frequently and bit flips occur at least 170 times less frequently. These findings represent the first confirmation of the expected error hierarchy necessary to concatenate dual-rail erasure qubits into a highly efficient erasure code.

Dual-rail encoding with superconducting cavities

  1. James D. Teoh,
  2. Patrick Winkel,
  3. Harshvardhan K. Babla,
  4. Benjamin J. Chapman,
  5. Jahan Claes,
  6. Stijn J. de Graaf,
  7. John W.O. Garmon,
  8. William D. Kalfus,
  9. Yao Lu,
  10. Aniket Maiti,
  11. Kaavya Sahay,
  12. Neel Thakur,
  13. Takahiro Tsunoda,
  14. Sophia H. Xue,
  15. Luigi Frunzio,
  16. Steven M. Girvin,
  17. Shruti Puri,
  18. and Robert J. Schoelkopf
The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computations. To this end, we introduce
the circuit-QED dual-rail qubit in which our physical qubit is encoded in the single-photon subspace of two superconducting cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers completely new capabilities. Using a single transmon ancilla, we describe a universal gate set that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors due to the cavity and transmon in all of these operations can be detected and converted to erasure errors, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit delivers an optimal hierarchy of errors and rates, and is expected to be well below the relevant QEC thresholds with today’s devices.

Error-detectable bosonic entangling gates with a noisy ancilla

  1. Takahiro Tsunoda,
  2. James D. Teoh,
  3. William D. Kalfus,
  4. Stijn J. de Graaf,
  5. Benjamin J. Chapman,
  6. Jacob C. Curtis,
  7. Neel Thakur,
  8. Steven M. Girvin,
  9. and Robert J. Schoelkopf
Bosonic quantum error correction has proven to be a successful approach for extending the coherence of quantum memories, but to execute deep quantum circuits, high-fidelity gates between
encoded qubits are needed. To that end, we present a family of error-detectable two-qubit gates for a variety of bosonic encodings. From a new geometric framework based on a „Bloch sphere“ of bosonic operators, we construct ZZL(θ) and eSWAP(θ) gates for the binomial, 4-legged cat, dual-rail and several other bosonic codes. The gate Hamiltonian is simple to engineer, requiring only a programmable beamsplitter between two bosonic qubits and an ancilla dispersively coupled to one qubit. This Hamiltonian can be realized in circuit QED hardware with ancilla transmons and microwave cavities. The proposed theoretical framework was developed for circuit QED but is generalizable to any platform that can effectively generate this Hamiltonian. Crucially, one can also detect first-order errors in the ancilla and the bosonic qubits during the gates. We show that this allows one to reach error-detected gate fidelities at the 10−4 level with today’s hardware, limited only by second-order hardware errors.