3D integration and packaging for solid-state qubits

  1. D. Rosenberg,
  2. S. Weber,
  3. D. Conway,
  4. D. Yost,
  5. J. Mallek,
  6. G. Calusine,
  7. R. Das,
  8. D. Kim,
  9. M. Schwartz,
  10. W. Woods,
  11. J.L. Yoder,
  12. and W. D. Oliver
Developing a packaging scheme that meets all of the requirements for operation of solid-state qubits in a cryogenic environment can be a formidable challenge. In this article, we discuss
work being done in our group as well as in the broader community, focusing on the role of 3D integration and packaging in quantum processing with solid-state qubits.

3D integrated superconducting qubits

  1. D. Rosenberg,
  2. D. Kim,
  3. R. Das,
  4. D. Yost,
  5. S. Gustavsson,
  6. D. Hover,
  7. P. Krantz,
  8. A. Melville,
  9. L. Racz,
  10. G. O. Samach,
  11. S. J. Weber,
  12. F. Yan,
  13. J. Yoder,
  14. A.J. Kerman,
  15. and W. D. Oliver
As the field of superconducting quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D
integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo>20μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.