Flux-Trapping Fluxonium Qubit

  1. Kotaro Hida,
  2. Kohei Matsuura,
  3. Shu Watanabe,
  4. and Yasunobu Nakamura
In pursuit of superconducting quantum computing, fluxonium qubits have recently garnered attention for their large anharmonicity and high coherence at the sweet spot. Towards the large-scale
integration of fluxonium qubits, a major obstacle is the need for precise external magnetic flux bias: To achieve high performance at its sweet spot, each qubit requires a DC bias line. However, such lines inductively coupled to the qubits bring in additional wiring overhead, crosstalk, heating, and decoherence, necessitating measures for mitigating the problems. In this work, we propose a flux-trapping fluxonium qubit, which, by leveraging fluxoid quantization, enables the optimal phase biasing without using external magnetic flux control at the operating temperature. We introduce the design and working principle, and demonstrate the phase biasing achieved through fluxoid quantization.

ZZ-Interaction-Free Single-Qubit-Gate Optimization in Superconducting Qubits

  1. Shu Watanabe,
  2. Yutaka Tabuchi,
  3. Kentaro Heya,
  4. Shuhei Tamate,
  5. and Yasunobu Nakamura
Overcoming the issue of qubit-frequency fluctuations is essential to realize stable and practical quantum computing with solid-state qubits. Static ZZ interaction, which causes a frequency
shift of a qubit depending on the state of neighboring qubits, is one of the major obstacles to integrating fixed-frequency transmon qubits. Here we propose and experimentally demonstrate ZZ-interaction-free single-qubit-gate operations on a superconducting transmon qubit by utilizing a semi-analytically optimized pulse based on a perturbative analysis. The gate is designed to be robust against slow qubit-frequency fluctuations. The robustness of the optimized gate spans a few MHz, which is sufficient for suppressing the adverse effects of the ZZ interaction. Our result paves the way for an efficient approach to overcoming the issue of ZZ interaction without any additional hardware overhead.