Simplified Josephson-junction fabrication process for reproducibly high-performance superconducting qubits

  1. A. Osman,
  2. J. Simon,
  3. A. Bengtsson,
  4. S. Kosen,
  5. P. Krantz,
  6. D. Perez,
  7. M. Scigliuzzo,
  8. Jonas Bylander,
  9. and A. Fadavi Roudsari
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5× 106). Current
shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type (PICT) junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4 and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7-2.5%. We show that 60-70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.