Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensionaltransmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
Quantum error correction will be an essential ingredient in realizing fault-tolerant quantum computing. However, most correction schemes rely on the assumption that errors are sufficientlyuncorrelated in space and time. In superconducting qubits this assumption is drastically violated in the presence of ionizing radiation, which creates bursts of high energy phonons in the substrate. These phonons can break Cooper-pairs in the superconductor and, thus, create quasiparticles over large areas, consequently reducing qubit coherence across the quantum device in a correlated fashion. A potential mitigation technique is to place large volumes of normal or superconducting metal on the device, capable of reducing the phonon energy to below the superconducting gap of the qubits. To investigate the effectiveness of this method we fabricate a quantum device with four nominally identical nanowire-based transmon qubits. On the device, half of the niobium-titanium-nitride ground plane is replaced with aluminum (Al), which has a significantly lower superconducting gap. We deterministically inject high energy phonons into the substrate by voltage biasing a galvanically isolated Josephson junction. In the presence of the low gap material, we find a factor of 2-5 less degradation in the injection-dependent qubit lifetimes, and observe that undesired excited qubit state population is mitigated by a similar factor. We furthermore turn the Al normal with a magnetic field, finding no change in the phonon-protection. This suggests that the efficacy of the protection in our device is not limited by the size of the superconducting gap in the Al ground plane. Our results provide a promising foundation for protecting superconducting qubit processors against correlated errors from ionizing radiation.
We report the detection of a gate-tunable kinetic inductance in a hybrid InAs/Al nanowire. For this purpose, we have embedded the nanowire into a quarter-wave coplanar waveguide resonatorand measured the resonance frequency of the circuit. We find that the resonance frequency can be changed via the gate voltage that controls the electron density of the proximitized semiconductor and thus the nanowire inductance. Applying Mattis-Bardeen theory, we extract the gate dependence of the normal state conductivity of the nanowire, as well as its superconducting gap. Our measurements complement existing characterization methods for hybrid nanowires and provide a new and useful tool for gate-controlled superconducting electronics.