Maintaining or even improving gate performance with growing numbers of parallel controlled qubits is a vital requirement towards fault-tolerant quantum computing. For superconductingquantum processors, though isolated one- or two-qubit gates have been demonstrated with high-fidelity, implementing these gates in parallel commonly show worse performance. Generally, this degradation is attributed to various crosstalks between qubits, such as quantum crosstalk due to residual inter-qubit coupling. An understanding of the exact nature of these crosstalks is critical to figuring out respective mitigation schemes and improved qubit architecture designs with low crosstalk. Here we give a theoretical analysis of quantum crosstalk impact on simultaneous gate operations in a qubit architecture, where fixed-frequency transmon qubits are coupled via a tunable bus, and sub-100-ns controlled-Z (CZ) gates can be realized by applying a baseband flux pulse on the bus. Our analysis shows that for microwave-driven single qubit gates, the dressing from qubit-qubit coupling can cause non-negligible cross-driving errors when qubits operate near frequency collision regions. During CZ gate operations, although unwanted near-neighbor interactions are nominally turned off, sub-MHz parasitic next-near-neighbor interactions involving spectator qubits can still exist, causing considerable leakage or control error when one operates qubit systems around these parasitic resonance points. To ensure high-fidelity simultaneous operations, this could rise a request to figure out a better way to balance the gate error from target qubit systems themselves and the error from non-participating spectator qubits. Overall, our analysis suggests that towards useful quantum processors, the qubit architecture should be examined carefully in the context of high-fidelity simultaneous gate operations in a scalable qubit lattice.
Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use the flip-chip technology to realizea modified transmon qubit, donated as the „flipmon“, whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. To further reduce the qubit footprint, we place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip which is galvanically connected with the single Josephson junction through an indium bump. The electric field participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 microns, and thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are measured in the range of 30-60 microseconds, which are comparable with that of traditional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface’s participation ratio increases significantly and may dominate the qubit’s decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.
By using the dry etching process of tantalum (Ta) film, we had obtained transmon qubit with the best lifetime (T1) 503 us, suggesting that the dry etching process can be adopted inthe following multi-qubit fabrication with Ta film. We also compared the relaxation and coherence times of transmons made with different materials (Ta, Nb and Al) with the same design and fabrication processes of Josephson junction, we found that samples prepared with Ta film had the best performance, followed by those with Al film and Nb film. We inferred that the reason for this difference was due to the different loss of oxide materials located at the metal-air interface.
High fidelity two-qubit gates are fundamental for scaling up the superconducting number. We use two qubits coupled via a frequency-tunable coupler which can adjust the coupling strength,and demonstrate the CZ gate using two different schemes, adiabatic and di-adiabatic methods. The Clifford based Randomized Benchmarking (RB) method is used to assess and optimize the CZ gate fidelity. The fidelity of adiabatic and di-adiabatic CZ gates are 99.53(8)% and 98.72(2)%, respectively. We also analyze the errors induced by the decoherence, which are 92% of total for adiabatic CZ gate and 46% of total for di-adiabatic CZ gates. The adiabatic scheme is robust against the operation error. But the di-adiabatic scheme is sensitive to the purity and operation errors. Comparing to 30 ns duration time of adiabatic CZ gate, the duration time of di-adiabatic CZ gate is 19 ns, revealing lower incoherence error rincoherent,Clfford = 0.0197(5) than r′incoherent,Clfford = 0.0223(3).