complexity of such devices, the requirements for reproducibility of their electrical properties across a chip have become stricter. Thus, the critical current Ic variation of the Josephson junction, as the most important electrical parameter, needs to be minimized. Critical current, in turn, is related to normal-state resistance the Ambegaokar-Baratoff formula, which can be measured at room temperature. Here, we focus on the dominant source of Josephson junction critical current non-uniformity junction area variation. We optimized Josephson junctions fabrication process and demonstrate resistance variation of 9.8−4.4% and 4.8−2.3% across 22×22 mm2 and 5×10 mm2 chip areas, respectively. For a wide range of junction areas from 0.008 μm2 to 0.12 μm2 we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. The developed process was tested on superconducting highly coherent transmon qubits (T1>100μs) and a nonlinear asymmetric inductive element parametric amplifier.