A.A. Pishchimova

Improving Josephson junction reproducibility for superconducting quantum circuits: shadow evaporation and oxidation

  1. D.O. Moskalev,
  2. E.V. Zikiy,
  3. A.A. Pishchimova,
  4. D.A. Ezenkova,
  5. N.S. Smirnov,
  6. A.I. Ivanov,
  7. N.D. Korshakov,
  8. and I.A. Rodionov
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where
Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale Al/AlOx/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate Al/AlOx/Al junction fabrication with the critical current variation (σ/Ic) less than 3.9% (from 150×200 to 150×600 nm2 area) and 7.7% (for 100×100 nm2 area) over 20×20 mm2 chip. Finally, we fabricate separately three 5×10 mm2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubit on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.
arxiv pdf

Improving Josephson junction reproducibility for superconducting quantum circuits: junction area fluctuation

  1. A.A. Pishchimova,
  2. N.S. Smirnov,
  3. D.A. Ezenkova,
  4. E.A. Krivko,
  5. E.V. Zikiy,
  6. D.O. Moskalev,
  7. A.I. Ivanov,
  8. N.D. Korshakov,
  9. and I.A. Rodionov
Josephson superconducting qubits and parametric amplifiers are prominent examples of superconducting quantum circuits that have shown rapid progress in recent years. With the growing
complexity of such devices, the requirements for reproducibility of their electrical properties across a chip have become stricter. Thus, the critical current Ic variation of the Josephson junction, as the most important electrical parameter, needs to be minimized. Critical current, in turn, is related to normal-state resistance the Ambegaokar-Baratoff formula, which can be measured at room temperature. Here, we focus on the dominant source of Josephson junction critical current non-uniformity junction area variation. We optimized Josephson junctions fabrication process and demonstrate resistance variation of 9.8−4.4% and 4.8−2.3% across 22×22 mm2 and 5×10 mm2 chip areas, respectively. For a wide range of junction areas from 0.008 μm2 to 0.12 μm2 we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. The developed process was tested on superconducting highly coherent transmon qubits (T1>100μs) and a nonlinear asymmetric inductive element parametric amplifier.
arxiv pdf