the Josephson junction fabrication process, producing a nonlinear inductance of the qubit. In this work, we demonstrate for 100 mm wafer decreasing of the room temperature resistance variation coefficient to 6.0% for 150×170 nm2 Al/AlOx/Al Josephson junction area and to 4.0% for 150×670 nm2 Al/AlOx/Al Josephson junction area. These results were achieved by the development of the shadow evaporation process model considering the Josephson junction area variation on the wafer. Our model allows us to provide the junction area variation coefficient of about 1.0% for Josephson junction characteristic dimensions from 100 nm to 700 nm. In addition, we show the junction oxidation technic optimization. Our improvements can be scalable on the wafer with a large diameter, which allows to manufacturing of the quantum processor with high reproducibility of electrical parameters.