Characterizing losses in InAs two-dimensional electron gas-based gatemon qubits

  1. William M. Strickland,
  2. Jaewoo Lee,
  3. Lukas Baker,
  4. Krishna Dindial,
  5. Bassel Heiba Elfeky,
  6. Mehdi Hatefipour,
  7. Peng Yu,
  8. Ido Levy,
  9. Vladimir E. Manucharyan,
  10. and Javad Shabani
The tunnelling of cooper pairs across a Josephson junction (JJ) allow for the nonlinear inductance necessary to construct superconducting qubits, amplifiers, and various other quantum
circuits. An alternative approach using hybrid superconductor-semiconductor JJs can enable a superconducting qubit architecture with full electric field control. Here we present continuous-wave and time-domain characterization of gatemon qubits based on an InAs 2DEG. We show that the qubit undergoes a vacuum Rabi splitting with a readout cavity and we drive coherent Rabi oscillations between the qubit ground and first excited states. We measure qubit coherence times to be T1= 100 ns over a 1.5 GHz tunable band. While various loss mechanisms are present in III-V gatemon circuits we detail future directions in enhancing the coherence times of qubit devices on this platform.

Voltage Activated Parametric Entangling Gates on Gatemons

  1. Yinqi Chen,
  2. Konstantin N. Nesterov,
  3. Hugh Churchill,
  4. Javad Shabani,
  5. Vladimir E. Manucharyan,
  6. and Maxim G. Vavilov
We describe the generation of entangling gates on superconductor-semiconductor hybrid qubits by ac voltage modulation of the Josephson energy. Our numerical simulations demonstrate
that the unitary error can be below 10−5 in a variety of 75-ns-long two-qubit gates (CZ, iSWAP, and iSWAP‾‾‾‾‾‾‾√) implemented using parametric resonance. We analyze the conditional ZZ phase and demonstrate that the CZ gate needs no further phase correction steps, while the ZZ phase error in SWAP-type gates can be compensated by choosing pulse parameters. With decoherence considered, we estimate that qubit relaxation time needs to exceed 70μs to achieve the 99.9% fidelity threshold.

Quasiparticle dynamics in epitaxial Al-InAs planar Josephson junctions

  1. Bassel Heiba Elfeky,
  2. William M. Strickland,
  3. Jaewoo Lee,
  4. James T. Farmer,
  5. Sadman Shanto,
  6. Azarin Zarassi,
  7. Dylan Langone,
  8. Maxim G. Vavilov,
  9. Eli M. Levenson-Falk,
  10. and Javad Shabani
Quasiparticle (QP) effects play a significant role in the coherence and fidelity of superconducting quantum circuits. The Andreev bound states of high transparency Josephson junctions
can act as low-energy traps for QPs, providing a mechanism for studying the dynamics and properties of both the QPs and the junction. We study the trapping and clearing of QPs from the Andreev bound states of epitaxial Al-InAs Josephson junctions incorporated in a superconducting quantum interference device (SQUID) galvanically shorting a superconducting resonator to ground. We use a neighboring voltage-biased Josephson junction to inject QPs into the circuit. Upon the injection of QPs, we show that we can trap and clear QPs when the SQUID is flux-biased. We examine effects of the microwave loss associated with bulk QP transport in the resonator, QP-related dissipation in the junction, and QP poisoning events. By monitoring the QP trapping and clearing in time, we study the dynamics of these processes and find a time-scale of few microseconds that is consistent with electron-phonon relaxation in our system and correlated QP trapping and clearing mechanisms. Our results highlight the QP trapping and clearing dynamics as well as the associated time-scales in high transparency Josephson junctions based fabricated on Al-InAs heterostructures.

Tunable Capacitor For Superconducting Qubits Using an InAs/InGaAs Heterostructure

  1. Nicholas Materise,
  2. Matthieu C. Dartiailh,
  3. William M. Strickland,
  4. Javad Shabani,
  5. and Eliot Kapit
Adoption of fast, parametric coupling elements has improved the performance of superconducting qubits, enabling recent demonstrations of quantum advantage in randomized sampling problems.
The development of low loss, high contrast couplers is critical for scaling up these systems. We present a blueprint for a gate-tunable coupler realized with a two-dimensional electron gas in an InAs/InGaAs heterostructure. Rigorous numerical simulations of the semiconductor and high frequency electromagnetic behavior of the coupler and microwave circuitry yield an on/off ratio of more than one order of magnitude. We give an estimate of the dielectric-limited loss from the inclusion of the coupler in a two qubit system, with coupler coherences ranging from a few to tens of microseconds.

Epitaxial Superconductor-Semiconductor Two-Dimensional Systems for Superconducting Quantum Circuits

  1. Joseph O'Connell Yuan,
  2. Kaushini S. Wickramasinghe,
  3. William M. Strickland,
  4. Matthieu C. Dartiailh,
  5. Kasra Sardashti,
  6. Mehdi Hatefipour,
  7. and Javad Shabani
Qubits on solid state devices could potentially provide the rapid control necessary for developing scalable quantum information processors. Materials innovation and design breakthroughs
have increased functionality and coherence of qubits substantially over the past two decades. Here we show by improving interface between InAs as a semiconductor and Al as a superconductor, one can reliably fabricate voltage-controlled Josephson junction field effect transistor (JJ-FET) that can be used as tunable qubits, resonators, and coupler switches. We find that band gap engineering is crucial in realizing a two-dimensional electron gas near the surface. In addition, we show how the coupling between the semiconductor layer and the superconducting contacts can affect qubit properties. We present the anharmonicity and coupling strengths from one and two-photon absorption in a quantum two level system fabricated with a JJ-FET.

Voltage-tunable superconducting resonators: a platform for random access quantum memory

  1. Kasra Sardashti,
  2. Matthieu C. Dartiailh,
  3. Joseph Yuan,
  4. Sean Hart,
  5. Patryk Gumann,
  6. and Javad Shabani
In quantum computing architectures, one important factor is the trade-off between the need to couple qubits to each other and to an external drive and the need to isolate them well
enough in order to protect the information for an extended period of time. In the case of superconducting circuits, one approach is to utilize fixed frequency qubits coupled to coplanar waveguide resonators such that the system can be kept in a configuration that is relatively insensitive to noise. Here, we propose a scalable voltage-tunable quantum memory (QuMem) design concept compatible with superconducting qubit platforms. Our design builds on the recent progress in fabrication of Josephson field effect transistors (JJ-FETs) which use InAs quantum wells. The JJ-FET is incorporated into a tunable coupler between a transmission line and a high-quality resonator in order to control the overall inductance of the coupler. A full isolation of the high-quality resonator can be achieved by turning off the JJ-FET. This could allow for long coherence times and protection of the quantum information inside the storage cavity. The proposed design would facilitate the implementation of random access memory for storage of quantum information in between computational gate operations.

Controlled-Z gate for transmon qubits coupled by semiconductor junctions

  1. Zhenyi Qi,
  2. Hong-Yi Xie,
  3. Javad Shabani,
  4. Vladimir E. Manucharyan,
  5. Alex Levchenko,
  6. and Maxim G. Vavilov
We analyze the coupling of two qubits via an epitaxial semiconducting junction. In particular, we consider three configurations that include pairs of transmons or gatemons as well as
gatemon-like two qubits formed by an epitaxial four-terminal junction. These three configurations provide an electrical control of the interaction between the qubits by applying voltage to a metallic gate near the semiconductor junction and can be utilized to naturally realize a controlled-Z gate (CZ). We calculate the fidelity and timing for such CZ gate. We demonstrate that in the absence of decoherence, the CZ gate can be performed under 50 ns with gate error below 10−4.