Fast single-qubit gates on weakly anharmonic transmons are limited by leakage to noncomputational states, and standard mitigations such as DRAG (derivative removal by adiabatic gate)act on the leakage amplitude at the end of the gate. We show that this endpoint amplitude and the transient leakage exposure accumulated during the gate are two distinct control objectives that can be assigned to separate modules. The endpoint is a single sample of the drive spectrum, |Λ̃ (η)|2; the exposure is a band integral about η and governs leakage under dephasing, and the spectral-null condition Λ̃ (η)=0 constrains only the former. We realize this split in a path–endpoint separation pulse (PESP): a path-shaping pulse suppresses the exposure, and a two-tone endpoint-cancellation pulse cancels the residual amplitude. For a 10 ns RX(π/2) gate at η/2π=0.2 GHz, in numerical simulations the path-shaping pulse reduces the dephasing exposure by ∼21% relative to cosine DRAG and the independently simulated Lindblad excess leakage by ∼20%, consistent with Pϕexcess≃γϕTP¯dephA, whereas matched-budget endpoint-only and spectral-null controls leave it essentially unchanged. The residual endpoint floor splits exactly into a |2⟩ back-action and a |3⟩ cascade, which the two tones cancel one-to-one, driving the floor at the path-exposure knee from ∼7×10−7 to ∼3×10−8 without perturbing the path. By separating transient exposure from endpoint leakage, PESP turns leakage suppression in fast weakly anharmonic gates into a modular, interpretable control problem: dephasing-induced leakage and the coherent residual error are reduced by separate, individually verifiable modules.
Fault-tolerant quantum computing requires large-scale superconducting processors, yet monolithic architectures face increasing constraints from wiring density, crosstalk, and fabricationyield. Modular superconducting platforms offer a scalable alternative, but achieving high-fidelity entangling gates between distant modules remains a central challenge, particularly for highly coherent fixed-frequency qubits. Here, we propose a distributed hardware architecture designed to overcome this bottleneck by employing a pair of double-transmon couplers (DTCs). By synchronously controlling the two DTCs stationed at opposite ends of a macroscopic cable, our scheme strongly suppresses residual static inter-module coupling while enabling on-demand activation of a non-local cross-Kerr interaction with an on/off ratio exceeding 106. Through comprehensive system-level numerical simulations incorporating realistic hardware parameters, we demonstrate that this mechanism can realize a remote controlled-Z (CZ) gate with a fidelity over 99.99\% between fixed-frequency transmons housed in separate packages interconnected by a 25 cm coaxial cable. These results establish a highly viable, hardware-efficient route toward high-performance distributed superconducting processors.
In superconducting quantum circuits, decoherence errors in qubits constitute a critical factor limiting quantum gate performance. To mitigate decoherence-induced gate infidelity, rapidimplementation of quantum gates is essential. Here we propose a scheme for rapid controlled-Z (CZ) gate implementation through energy-level engineering, which leverages Rabi oscillations between the |11> state and the superposition state in a tunable-coupler architecture. Numerical simulations achieved a 17 ns nonadiabatic CZ gate with fidelity over 99.99%. We further investigated the performance of the CZ gate in the presence of anharmonicity offsets. The results demonstrate that a high-fidelity CZ gate with an error rate below 10^-4 remains achievable even with finite anharmonicity variations. Furthermore, the detrimental impact of spectator qubits in different quantum states on the fidelity of CZ gate is effectively suppressed by incorporating a tunable coupler. This scheme exhibits potential for extending the circuit execution depth constrained by coherence time limitations.
Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA toolscannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.
Due to its significant application in reducing algorithm depth, fSim gates have attracted a lot of attention, while one-step implementation of fSim gates remains an unresolved issue.In this manuscript, we propose a one-step implementation of holonomic fSim gates in a tunable superconducting circuit based on the three lowest energy levels. Numerical simulations demonstrate the feasibility of our scheme. This scheme may provide a promising path toward quantum computation and simulation.