Dissipation remains a central obstacle to improving superconducting quantum circuits, yet the microscopic origins of loss in widely used materials platforms are not fully understood.Here, we report the observation of interface piezoelectricity-induced dissipation in superconducting qubits fabricated on high-resistivity silicon. Our devices use a transmon qubit with a shunt capacitor that simultaneously serves as an interdigital transducer embedded in a surface acoustic wave resonator. By tuning the qubit transition into resonance with discrete mechanical modes, we observe up to a factor-of-two reduction in qubit lifetime, consistent with energy exchange between the qubit and mechanical modes mediated by piezoelectric coupling at the aluminum-silicon interface. Our findings provide direct evidence for interface piezoelectricity as a distinct loss channel in superconducting qubits. Combined with multiphysics simulations, these findings suggest that interface piezoelectric loss can dominate over loss from two-level systems at sufficiently high frequencies.
We demonstrate a sapphire machining process integrated with intermediate-scale quantum processors. The process allows through-substrate electrical connections, necessary for low-frequencymode-mitigation, as well as signal-routing, which are vital as quantum computers scale in qubit number, and thus dimension. High-coherence qubits are required to build fault-tolerant quantum computers and so material choices are an important consideration when developing a qubit technology platform. Sapphire, as a low-loss dielectric substrate, has shown to support high-coherence qubits. In addition, recent advances in material choices such as tantalum and titanium-nitride, both deposited on a sapphire substrate, have demonstrated qubit lifetimes exceeding 0.3 ms. However, the lack of any process equivalent of deep-silicon etching to create through-substrate-vias in sapphire, or to inductively shunt large dies, has limited sapphire to small-scale processors, or necessitates the use of chiplet architecture. Here, we present a sapphire machining process that is compatible with high-coherence qubits. This technique immediately provides a means to scale QPUs with integrated mode-mitigation, and provides a route toward the development of through-sapphire-vias, both of which allow the advantages of sapphire to be leveraged as well as facilitating the use of sapphire-compatible materials for large-scale QPUs.
Superconducting qubits are a promising route to achieving large-scale quantum computers. A key challenge in realising large-scale superconducting quantum processors involves mitigatingfrequency collisions. In this paper, we present an approach to tuning fixed-frequency qubits with the use of an electron beam to locally anneal the Josephson junction. We demonstrate the ability to both increase and decrease the junction barrier resistance. The technique shows an improvement in wafer scale frequency targetting by assessing the frequency collisions in our qubit architecture. Coherence measurements are also done to evaluate the performance before and after tuning. The tuning process utilises a standard electron beam lithography system, ensuring reproducibility and implementation by any group capable of fabricating these Josephson junctions. This technique has the potential to significantly improve the performance of large-scale quantum computing systems, thereby paving the way for the future of quantum computing.