Verena Feulner

Scalable Fluxonium-Transmon Architecture for Error Corrected Quantum Processors

  1. Lukas Heunisch,
  2. Longxiang Huang,
  3. Stephan Tasler,
  4. Johannes Schirk,
  5. Florian Wallner,
  6. Verena Feulner,
  7. Bijita Sarma,
  8. Klaus Liegener,
  9. Christian M. F. Schneider,
  10. Stefan Filipp,
  11. and Michael J. Hartmann
We propose a hybrid quantum computing architecture composed of alternating fluxonium and transmon qubits, that are coupled via transmon tunable couplers. We show that this system offers
excellent scaling properties, characterized by engineered zero ZZ-crosstalk in the idle regime, a substantial reduction of level-crowding challenges through the alternating arrangement of different qubit types within the lattice, and parameter regimes that circumvent the capacitive loading problem commonly associated with fluxoniums. In numerical simulations, we show a parametrically driven CZ-gate that achieves a closed-system infidelity that is orders of magnitude below the coherence limit for gate durations ≳30ns using a two-tone flux pulse on the tunable coupler. Furthermore, we show that this gate scheme retains its fidelity in the presence of spectator qubits, making it a scalable solution for large lattices. Moreover, for the implementation of error correcting codes, our approach can leverage the long coherence times and large non-linearities of fluxoniums as data qubits, while fixed-frequency transmons with established readout techniques can serve as measurement ancillas.
arxiv pdf

Optimizing Superconducting Three-Qubit Gates for Surface-Code Error Correction

  1. Stephan Tasler,
  2. Josias Old,
  3. Lukas Heunisch,
  4. Verena Feulner,
  5. Timo Eckstein,
  6. Markus Müller,
  7. and Michael J. Hartmann
Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications.
Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates, and is repeated many times during a computation. To improve QEC performance, it is thus beneficial to make the stabilizer readout faster and less prone to fault-tolerance-breaking errors. Here we design a 3-qubit CZZ gate for superconducting transmon qubits that maps the parity of two data qubits onto one measurement qubit in a single step. We find that the gate can be executed in a duration of 35ns with a fidelity of F=99.96%. To optimize the gate, we use an error model obtained from the microscopic gate simulation to systematically suppress Pauli errors that are particularly harmful to the QEC protocol. Using this error model, we investigate the implementation of this 3-qubit gate in a surface code syndrome readout schedule. We find that for the rotated surface code, the implementation of CZZ gates increases the error threshold by nearly 50\% to ≈1.2% and decreases the logical error rate, in the experimental relevant regime, by up to one order of magnitude, compared to the standard CZ readout protocol. We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found. This opens a new perspective for below-threshold surface-code error correction, where it can be advantageous to use multi-qubit gates instead of two-qubit gates to obtain a better QEC performance.
arxiv pdf