Rémi Rousseau

Hyperinductance based on stacked Josephson junctions

  1. Paul Manset,
  2. José Palomo,
  3. Aurélien Schmitt,
  4. Kyrylo Gerashchenko,
  5. Rémi Rousseau,
  6. Himanshu Patange,
  7. Patrick Abgrall,
  8. Emmanuel Flurin,
  9. Samuel Deléglise,
  10. Thibaut Jacqmin,
  11. and Léo Balembois
Superinductances are superconducting circuit elements that combine a large inductance with a low parasitic capacitance to ground, resulting in a characteristic impedance exceeding the
resistance quantum RQ=h/(2e)2≃6.45kΩ. In recent years, these components have become key enablers for emerging quantum circuit architectures. However, achieving high characteristic impedance while maintaining scalability and fabrication robustness remains a major challenge. In this work, we present two fabrication techniques for realizing superinductances based on vertically stacked Josephson junctions. Using a multi-angle Manhattan (MAM) process and a zero-angle (ZA) evaporation technique — in which junction stacks are connected pairwise using airbridges — we fabricate one-dimensional chains of stacks that act as high-impedance superconducting transmission lines. Two-tone microwave spectroscopy reveals the expected n‾√ scaling of the impedance with the number of junctions per stack. The chain fabricated using the ZA process, with nine junctions per stack, achieves a characteristic impedance of ∼16kΩ, a total inductance of 5.9μH, and a maximum frequency-dependent impedance of 50kΩ at 1.4 GHz. Our results establish junction stacking as a scalable, robust, and flexible platform for next-generation quantum circuits requiring ultra-high impedance environments.
arxiv pdf

Enhancing dissipative cat qubit protection by squeezing

  1. Rémi Rousseau,
  2. Diego Ruiz,
  3. Emanuele Albertinale,
  4. Pol d'Avezac,
  5. Danielius Banys,
  6. Ugo Blandin,
  7. Nicolas Bourdaud,
  8. Giulio Campanaro,
  9. Gil Cardoso,
  10. Nathanael Cottet,
  11. Charlotte Cullip,
  12. Samuel Deléglise,
  13. Louise Devanz,
  14. Adam Devulder,
  15. Antoine Essig,
  16. Pierre Février,
  17. Adrien Gicquel,
  18. Élie Gouzien,
  19. Antoine Gras,
  20. Jérémie Guillaud,
  21. Efe Gümüş,
  22. Mattis Hallén,
  23. Anissa Jacob,
  24. Paul Magnard,
  25. Antoine Marquet,
  26. Salim Miklass,
  27. Théau Peronnin,
  28. Stéphane Polis,
  29. Felix Rautschke,
  30. Ulysse Réglade,
  31. Julien Roul,
  32. Jeremy Stevens,
  33. Jeanne Solard,
  34. Alexandre Thomas,
  35. Jean-Loup Ville,
  36. Pierre Wan-Fat,
  37. Raphaël Lescanne,
  38. Zaki Leghtas,
  39. Joachim Cohen,
  40. Sébastien Jezouin,
  41. and Anil Murani
Dissipative cat-qubits are a promising architecture for quantum processors due to their built-in quantum error correction. By leveraging two-photon stabilization, they achieve an exponentially
suppressed bit-flip error rate as the distance in phase-space between their basis states increases, incurring only a linear increase in phase-flip rate. This property substantially reduces the number of qubits required for fault-tolerant quantum computation. Here, we implement a squeezing deformation of the cat qubit basis states, further extending the bit-flip time while minimally affecting the phase-flip rate. We demonstrate a steep reduction in the bit-flip error rate with increasing mean photon number, characterized by a scaling exponent γ=4.3, rising by a factor of 74 per added photon. Specifically, we measure bit-flip times of 22 seconds for a phase-flip time of 1.3 μs in a squeezed cat qubit with an average photon number n¯=4.1, a 160-fold improvement in bit-flip time compared to a standard cat. Moreover, we demonstrate a two-fold reduction in Z-gate infidelity, with an estimated phase-flip probability of ϵX=0.085 and a bit-flip probability of ϵZ=2.65⋅10−9 which confirms the gate bias-preserving property. This simple yet effective technique enhances cat qubit performances without requiring design modification, moving multi-cat architectures closer to fault-tolerant quantum computation.
arxiv pdf