Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunitiesand challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by indium bumps by atmospheric thermocompression bonding. The temperature dependence of the inter-chip thermal resistance follows the power law of αT−3, with α=7.7−15.4 K4 μm2/nW and a thermal contact area of 0.306 mm2. The T−3 relation indicates phononic interfacial thermal resistance, which is supported by the vanishing electrical thermal conduction due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck, which can be detrimental for some applications, but it can also be harnessed. We provide a study of the latter case by simulating the performance of solid-state junction microrefrigerator where we use the measured thermal resistance value.