Kieran Dalton

Resource-Efficient Cross-Platform Verification with Modular Superconducting Devices

  1. Kieran Dalton,
  2. Johannes Knörzer,
  3. Finn Hoehne,
  4. Yongxin Song,
  5. Alexander Flasby,
  6. Dante Colao Zanuz,
  7. Mohsen Bahrami Panah,
  8. Ilya Besedin,
  9. Jean-Claude Besse,
  10. and Andreas Wallraff
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance
within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state — a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two three-qubit modules on a single carrier chip, with connectivity for intra- and inter-module entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an inter-module two-qubit gate enables sub-exponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of four for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
arxiv pdf

Performance Characterization of a Multi-Module Quantum Processor with Static Inter-Chip Couplers

  1. Graham J. Norris,
  2. Kieran Dalton,
  3. Dante Colao Zanuz,
  4. Alexander Rommens,
  5. Alexander Flasby,
  6. Mohsen Bahrami Panah,
  7. François Swiadek,
  8. Colin Scarato,
  9. Christoph Hellings,
  10. Jean-Claude Besse,
  11. and Andreas Wallraff
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which
circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of 9×10−3 in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of 6×10−4, consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of 7×10−3 extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.
arxiv pdf