High Coherence in a Tileable 3D Integrated Superconducting Circuit Architecture

  1. Peter A. Spring,
  2. Shuxiang Cao,
  3. Takahiro Tsunoda,
  4. Giulio Campanaro,
  5. Simone D. Fasciati,
  6. James Wills,
  7. Vivek Chidambaram,
  8. Boris Shteynas,
  9. Mustafa Bakr,
  10. Paul Gow,
  11. Lewis Carpenter,
  12. James Gates,
  13. Brian Vlastakis,
  14. and Peter J. Leek
We report high qubit coherence as well as low crosstalk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to 2D lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring non-galvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times T1=149(38) μs, pure echoed dephasing times Tϕ,e=189(34) μs, and single-qubit gate fidelities F=99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.
arxiv pdf

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