Seungyong Hahn

Characterization of Broadband Purcell Filters with Compact Footprint for Fast Multiplexed Superconducting Qubit Readout

  1. Seong Hyeon Park,
  2. Gahyun Choi,
  3. Gyunghun Kim,
  4. Jaehyeong Jo,
  5. Bumsung Lee,
  6. Geonyoung Kim,
  7. Kibog Park,
  8. Yong-Ho Lee,
  9. and Seungyong Hahn
Engineering the admittance of external environments connected to superconducting qubits is essential, as increasing the measurement speed introduces spontaneous emission loss to superconducting
qubits, known as Purcell loss. Here, we report a broad bandwidth Purcell filter design within a small footprint, which effectively suppresses Purcell loss without losing the fast measurement speed. We characterize the filter’s frequency response at 4.3 K and also estimate Purcell loss suppression by finite-element-method simulations of superconducting planar circuit layouts with the proposed filter design. The measured bandwidth is over 790 MHz within 0.29 mm2 while the estimated lifetime enhancement can be over 5000 times with multiple Purcell filters. The presented filter design is expected to be easily integrated on existing superconducting quantum circuits for fast and multiplexed readout without occupying large footprint.
arxiv pdf

Shape optimization of superconducting transmon qubit for low surface dielectric loss

  1. Sungjun Eun,
  2. Seong Hyeon Park,
  3. Kyungsik Seo,
  4. Kibum Choi,
  5. and Seungyong Hahn
Surface dielectric loss of superconducting transmon qubit is believed as one of the dominant sources of decoherence. Reducing surface dielectric loss of superconducting qubit is known
to be a great challenge for achieving high quality factor and a long relaxation time (T1). Changing the geometry of capacitor pads and junction wire of transmon qubit makes it possible to engineer the surface dielectric loss. In this paper, we present the shape optimization approach for reducing Surface dielectric loss in transmon qubit. The capacitor pad and junction wire of the transmon qubit are shaped as spline curves and optimized through the combination of the finite-element method and global optimization algorithm. Then, we compared the surface participation ratio, which represents the portion of electric energy stored in each dielectric layer and proportional to two-level system (TLS) loss, of optimized structure and existing geometries to show the effectiveness of our approach. The result suggests that the participation ratio of capacitor pad, and junction wire can be reduced by 16% and 26% compared to previous designs through shape optimization, while overall footprint and anharmonicity maintain acceptable value. As a result, the TLS-limited quality factor and corresponding T1 were increased by approximately 21.6%.
arxiv pdf