L. Nebrich

3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

  1. T. Mayer,
  2. H. Bender,
  3. S. J. K. Lang,
  4. Z. Luo,
  5. J. Weber,
  6. C. Moran Guizan,
  7. C. Dhieb,
  8. D. Zahn,
  9. L. Schwarzenbach,
  10. W. Hell,
  11. M. Andronic,
  12. A. Drost,
  13. K. Neumeier,
  14. W. Lerch,
  15. L. Nebrich,
  16. A. Hagelauer,
  17. I. Eisele,
  18. R.N. Pereira,
  19. and C. Kutter
In this article, we present a technology development of a superconducting qubit device 3D-integrated by flip-chip-bonding and processed following CMOS fabrication standards and contamination
rules on 200 mm wafers. We present the utilized proof-of-concept chip designs for qubit- and carrier chip, as well as the respective front-end and back-end fabrication techniques. In characterization of the newly developed microbump technology based on metallized KOH-etched Si-islands, we observe a superconducting transition of the used metal stacks and radio frequency (RF) signal transfer through the bump connection with negligible attenuation. In time-domain spectroscopy of the qubits we find high yield qubit excitation with energy relaxation times of up to 15 us.
arxiv pdf