Transmons are widely adopted in quantum computing architectures for their engineered insensitivity to charge noise and correspondingly long relaxation times. Despite this advantage,transmons often exhibit large fluctuations in dephasing times across different devices and also within qubits on the same device. Existing transmon qubits are assumed to be insensitive to charge noise. However, very little recent attention has been paid to the dependence of dephasing on the local charge environment. In this study, we see fluctuations in the dephasing time, Tϕ, which correlate to charge offset. While charge offset fluctuations are slow, parity switches are fast processes tied to the charge offset and can affect Tϕ in Ramsey experiments. We implement a protocol to detect parity switching events using single-shot methods, which are interleaved within a Ramsey measurement. We find that events that remain in the same parity state have a higher T2 than measurements averaged over both parities. Our results show that transmons can be limited by charge-noise, even with EJ/EC≈50. Consequently, parity flip rates must be considered as a device characterization metric.
This work presents a combined analytical and simulation-based study of a 3D-integrated quantum chip architecture. We model a flip-chip-inspired structure by stacking two superconductingqubits fabricated on separate high-resistivity silicon substrates through a dielectric interlayer. Utilizing \emph{rigorous} Ansys High-Frequency Structure Simulator (HFSS) simulations and analytical models from microwave engineering and quantum theory, we evaluate key quantum metrics such as eigenfrequencies, Q-factors, decoherence times, anharmonicity, cross-Kerr, participation ratios, and qubit coupling energy to describe the performance of the quantum device as a function of integration parameters. The integration parameters include the thickness and the quality of the dielectric interlayer. For detuned qubits, these metrics remain mostly invariant with respect to the substrate separation. However, introducing dielectric interlayer loss decreases the qubit quality factor, which consequentially degrades the relaxation time of the qubit. It is found that for the structure studied in this work, the stacked chip distance can be as small as 0.5mm. These findings support the viability of 3D quantum integration as a scalable alternative to planar architectures, while identifying key limitations in qubit coherence preservation due to lossy interlayer materials.