The progress witnessed within the field of quantum computing has been enabled by the identification and understanding of interactions between the state of the quantum bit (qubit) andthe materials within its environment. Beginning with an introduction of the parameters used to differentiate various quantum computing approaches, we discuss the evolution of the key components that comprise superconducting qubits, where the methods of fabrication can play as important a role as the composition in dictating the overall performance. We describe several mechanisms that are responsible for the relaxation or decoherence of superconducting qubits and the corresponding methods that can be utilized to characterize their influence. In particular, the effects of dielectric loss and its manifestation through the interaction with two-level systems (TLS) are discussed. We elaborate on the methods that are employed to quantify dielectric loss through the modeling of energy flowing through the surrounding dielectric materials, which can include contributions due to both intrinsic TLS and extrinsic aspects, such as those generated by processing. The resulting analyses provide insight into identifying the relative participation of specific sections of qubit designs and refinements in construction that can mitigate their impact on qubit quality factors. Additional prominent mechanisms that can lead to energy relaxation within qubits are presented along with experimental techniques which assess their importance. We close by highlighting areas of future research that should be addressed to help facilitating the successful scaling of superconducting quantum computing.
A strategy aimed at decreasing dielectric loss in coplanar waveguides (CPW) and qubits involves the creation of trenches in the underlying substrate within the gaps of the overlyingmetallization. Participation of contamination layers residing on surfaces and interfaces in these designs can be reduced due to the change in the effective dielectric properties between the groundplane and conductor metallization. Although finite element method approaches have been previously applied to quantify this decrease, an analytical method is presented that can uniquely address geometries possessing small to intermediate substrate trench depths. Conformal mapping techniques produce transformed CPW and qubit geometries without substrate trenching but a non-uniform contamination layer thickness. By parametrizing this variation, one can calculate surface participation through the use of a two-dimensional, analytical approximation that properly captures singularities in the electric field intensity near the metallization corners and edges. Examples demonstrate two regimes with respect to substrate trench depth that capture an initial increase in substrate-to-air surface participation due to the trench sidewalls and an overall decrease in surface participation due to the reduction in the effective dielectric constant, and are compared to experimental measurements to extract loss tangents on this surface.
Superconducting qubits are sensitive to a variety of loss mechanisms which include dielectric loss from interfaces. The calculation of participation near the key interfaces of planardesigns can be accomplished through an analytical description of the electric field density based on conformal mapping. In this way, a two-dimensional approximation to coplanar waveguide and capacitor designs produces values of the participation as a function of depth from the top metallization layer as well as the volume participation within a given thickness from this surface by reducing the problem to a surface integration over the region of interest. These quantities are compared to finite element method numerical solutions, which validate the values at large distances from the coplanar metallization but diverge near the edges of the metallization features due to the singular nature of the electric fields. A simple approximation to the electric field energy at shallow depths (relative to the waveguide width) is also presented that closely replicates the numerical results based on conformal mapping. These techniques are applied to the calculation of surface participation within a transmon qubit design, where the effects due to shunting capacitors can be easily integrated with those associated with metallization comprising the local environment of the qubit junction.