The true-differential superconductor on-chip amplifier has complementary outputs that float with respect to chip ground. This improves signal integrity and compatibility with the receivingsemiconductor stage. Both source-terminated and non-source-terminated designs producing 4mV demonstrated rejection of a large common mode interference in the package. Measured margins are ±8.5% on the output bias, and ±28% on AC clock amplitude. Waveforms and eye diagrams are taken at 2.9-10Gb/s. Direct measurement of bit-error rates are better than the resolution limit of 1e-12 at 2.9Gb/s, and better than 1e-9 at 10Gb/s.
A circuit-simulation-based method is used to determine the thermally-induced bit error rate of superconducting logic circuits. Simulations are used to evaluate the multidimensionalGaussian integral across noise current sources attached to the active devices. The method is data-assisted and has predictive power. Measurement determines the value of a single parameter, effective noise bandwidth, for each error mechanism. The errors in the distributed networks of comparator-free RQL logic nucleate across multiple Josephson junctions, so the effective critical current is about three times that of the individual devices. The effective noise bandwidth is only 6-23% of the junction plasma frequency at a modest clock rate of 3.4GHz, which is 1% of the plasma frequency. This analysis shows the ways measured bit error rate comes out so much lower than simplistic estimates based on isolated devices.