Using inductive Energy Participation Ratio for Superconducting Quantum Chip Characterization

We have developed an inductive energy participation ratio (iEPR) method and a concise procedure for superconducting quantum chip layout simulation and verification that is increasingly indispensable in large-scale, fault-tolerant quantum computing. It can be utilized to extract the characteristic parameters and the bare Hamiltonian of the layout in an efficient way. In theory, iEPR sheds light on the deep-seated relationship between energy distribution and representation transformation. As a stirring application, we apply it to a typical quantum chip layout, obtaining all the crucial characteristic parameters in one step that would be extremely challenging through the existing methods. Our work is expected to significantly improve the simulation and verification techniques and takes an essential step toward quantum electronic design automation.