CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

  1. T. Mayer,
  2. J. Weber,
  3. E. Music,
  4. C. Moran Guizan,
  5. S. J. K. Lang,
  6. L. Schwarzenbach,
  7. C. Dhieb,
  8. B. Kiliclar,
  9. A. Maiwald,
  10. Z. Luo,
  11. W. Lerch,
  12. D. Zahn,
  13. I. Eisele,
  14. R.N. Pereira,
  15. and C. Kutter
We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.
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