Quantum computing can become scalable through error correction, but logical error rates only decrease with system size when physical errors are sufficiently uncorrelated. During computation,unused high energy levels of the qubits can become excited, creating leakage states that are long-lived and mobile. Particularly for superconducting transmon qubits, this leakage opens a path to errors that are correlated in space and time. Here, we report a reset protocol that returns a qubit to the ground state from all relevant higher level states. We test its performance with the bit-flip stabilizer code, a simplified version of the surface code for quantum error correction. We investigate the accumulation and dynamics of leakage during error correction. Using this protocol, we find lower rates of logical errors and an improved scaling and stability of error suppression with increasing qubit number. This demonstration provides a key step on the path towards scalable quantum computing.
We demonstrate diabatic two-qubit gates with Pauli error rates down to 4.3(2)⋅10−3 in as fast as 18 ns using frequency-tunable superconducting qubits. This is achieved by synchronizingthe entangling parameters with minima in the leakage channel. The synchronization shows a landscape in gate parameter space that agrees with model predictions and facilitates robust tune-up. We test both iSWAP-like and CPHASE gates with cross-entropy benchmarking. The presented approach can be extended to multibody operations as well.
Superconducting qubits are an attractive platform for quantum computing since they have demonstrated high-fidelity quantum gates and extensibility to modest system sizes. Nonetheless,an outstanding challenge is stabilizing their energy-relaxation times, which can fluctuate unpredictably in frequency and time. Here, we use qubits as spectral and temporal probes of individual two-level-system defects to provide direct evidence that they are responsible for the largest fluctuations. This research lays the foundation for stabilizing qubit performance through calibration, design, and fabrication.
Complex integrated circuits require multiple wiring layers. In complementary metal-oxide-semiconductor (CMOS) processing, these layers are robustly separated by amorphous dielectrics.These dielectrics would dominate energy loss in superconducting integrated circuits. Here we demonstrate a procedure that capitalizes on the structural benefits of inter-layer dielectrics during fabrication and mitigates the added loss. We separate and support multiple wiring layers throughout fabrication using SiO2 scaffolding, then remove it post-fabrication. This technique is compatible with foundry level processing and the can be generalized to make many different forms of low-loss multi-layer wiring. We use this technique to create freestanding aluminum vacuum gap crossovers (airbridges). We characterize the added capacitive loss of these airbridges by connecting ground planes over microwave frequency λ/4 coplanar waveguide resonators and measuring resonator loss. We measure a low power resonator loss of ∼3.9×10−8 per bridge, which is 100 times lower than dielectric supported bridges. We further characterize these airbridges as crossovers, control line jumpers, and as part of a coupling network in gmon and fuxmon qubits. We measure qubit characteristic lifetimes (T1’s) in excess of 30 μs in gmon devices.