Calibration of the cross-resonance two-qubit gate between directly-coupled transmons

  1. A. D. Patterson,
  2. J. Rahamim,
  3. T. Tsunoda,
  4. P. Spring,
  5. S. Jebari,
  6. K. Ratter,
  7. M. Mergenthaler,
  8. G. Tancredi,
  9. B. Vlastakis,
  10. M. Esposito,
  11. and P. J. Leek
Quantum computation requires the precise control of the evolution of a quantum system, typically through application of discrete quantum logic gates on a set of qubits. Here, we use
the cross-resonance interaction to implement a gate between two superconducting transmon qubits with a direct static dispersive coupling. We demonstrate a practical calibration procedure for the optimization of the gate, combining continuous and repeated-gate Hamiltonian tomography with step-wise reduction of dominant two-qubit coherent errors through mapping to microwave control parameters. We show experimentally that this procedure can enable a ZX^−π/2 gate with a fidelity F=97.0(7)%, measured with interleaved randomized benchmarking. We show this in a architecture with out-of-plane control and readout that is readily extensible to larger scale quantum circuits.

Double-sided coaxial circuit QED with out-of-plane wiring

  1. J. Rahamim,
  2. T. Behrle,
  3. M. J. Peterer,
  4. A. Patterson,
  5. P. Spring,
  6. T. Tsunoda,
  7. R. Manenti,
  8. G. Tancredi,
  9. and P. J. Leek
Superconducting circuits are well established as a strong candidate platform for the development of quantum computing. In order to advance to a practically useful level, architectures
are needed which combine arrays of many qubits with selective qubit control and readout, without compromising on coherence. Here we present a coaxial circuit QED architecture in which qubit and resonator are fabricated on opposing sides of a single chip, and control and readout wiring are provided by coaxial wiring running perpendicular to the chip plane. We present characterisation measurements of a fabricated device in good agreement with simulated parameters and demonstrating energy relaxation and dephasing times of T1=4.1μs and T2=5.7μs respectively. The architecture allows for scaling to large arrays of selectively controlled and measured qubits with the advantage of all wiring being out of the plane.