Simplified Josephson-junction fabrication process for reproducibly high-performance superconducting qubits

  1. A. Osman,
  2. J. Simon,
  3. A. Bengtsson,
  4. S. Kosen,
  5. P. Krantz,
  6. D. Perez,
  7. M. Scigliuzzo,
  8. Jonas Bylander,
  9. and A. Fadavi Roudsari
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5× 106). Current
shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type (PICT) junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4 and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7-2.5%. We show that 60-70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.

A Quantum Instruction Set Implemented on a Superconducting Quantum Processor

  1. M. Kjaergaard,
  2. M. E. Schwartz,
  3. A. Greene,
  4. G. O. Samach,
  5. A. Bengtsson,
  6. M. O'Keeffe,
  7. C. M. McNally,
  8. J. Braumüller,
  9. D. K. Kim,
  10. P. Krantz,
  11. M. Marvian,
  12. A. Melville,
  13. B. M. Niedzielski,
  14. Y. Sung,
  15. R. Winik,
  16. J. Yoder,
  17. D. Rosenberg,
  18. K. Obenland,
  19. S. Lloyd,
  20. T. P. Orlando,
  21. I. Marvian,
  22. S. Gustavsson,
  23. and W. D. Oliver
A quantum algorithm consists of a sequence of operations and measurements applied to a quantum processor. To date, the instruction set which defines this sequence has been provided
by a classical computer and passed via control hardware to the quantum processor. Here, we demonstrate the first experimental realization of a quantum instruction set, in which a fixed sequence of classically-defined gates perform an operation that is fully determined only by a quantum input to the fixed sequence. Specifically, we implement the density matrix exponentiation algorithm, which consumes N copies of the instruction state ρ to approximate the operation e−iρθ (θ an arbitrary angle). Our implementation relies on a 99.7\% fidelity controlled-phase gate between two superconducting transmon qubits. We achieve an average algorithmic fidelity ≈0.9, independent of the setting of ρ, to circuit depth nearly 90. This new paradigm for quantum instructions has applications to resource-efficient protocols for validating entanglement spectra, principal component analysis of large quantum states, and universal quantum emulation.

3D integrated superconducting qubits

  1. D. Rosenberg,
  2. D. Kim,
  3. R. Das,
  4. D. Yost,
  5. S. Gustavsson,
  6. D. Hover,
  7. P. Krantz,
  8. A. Melville,
  9. L. Racz,
  10. G. O. Samach,
  11. S. J. Weber,
  12. F. Yan,
  13. J. Yoder,
  14. A.J. Kerman,
  15. and W. D. Oliver
As the field of superconducting quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D
integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo>20μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.